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Hi A.K,
In the state machine, you can see that the LD_DATA_COUNT and LD_ADDR_COUNT are set to 2047 and 255 respectively. This means that DATA_CNT_HIT (data counter hit) becomes valid only when Address Counter is counted and hit 8 times. So, WR_DATA_WAIT -> WR_DATA and back to WR_DATA to WR_DATA_WAIT should take place 8 times for the ADDR_COUNT to hit. (Note that WR_DATA state performs both COUNT ADDR and COUNT DATA operations).
In the Timing scenarion you created, you just do this once and want it transition to COUNT_HIT state which is reached only when DATA_COUNT is hit.
That is why the error was thrown.
Regards,
- Madhu Sudhan
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Hi Madhu Sudhan,
The DMA buffer size is 16×1024byte and ADDR_CNT_HIT when 1024byte data transfered.What is DATA_CNT_HIT counter use for?
Thanks,
-Ran Liang
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Hi A.K,
You cannot assert it by force. Sorry for inconvenience.
For testing purpose alone, you can remove the DMA_RDY_TH0 from the transition equation and do the timing simulation.
Regards,
- Madhu Sudhan
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Hi Madhu Sudhan,
Thanks! It simulates fine now without DMA flag. I also tried with IN_REG_VALID which simulated also fine..
Regards!