Hi~ A few months ago I bought two CYUSB3KIT-003 Cypress Development Kits.
I try to learn GPIFII transmission function and try run Designing a GPIF™ II Master Interface example(application note: AN87216)
FX3 Back-to-Back Setup Using CYUSB3KIT-003 like AN87216 Figure 26.
I test Master transform data to Slave was Pass (FX3 Firmware Master = Autoslave.img Slave = AutoSlave.img)
For example, Master-side transfer data 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B total of 8 Bytes to Slave.
Slave-side Receives the correct data from Master.
But test Slave transform data transform data to Master was Fail.
For example, Slave-side transfer data 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B total of 8 Bytes to Master.
But Master-side Receives the error data from Slave. And can not be expected.
What can I do for next step??
Did you check if the flag / other control signals behave as expected? There could be a connection issue in any of these crucial signals.
Just in case, please create a Tech Support case with us so that one of our engineers can investigate the issue.
I am facing the same issue. Could you able to resolve this? Please share the solution.