I am supposed to create a GPIF II state machine on a master FX3 (CYUSB3014) USB Super Speed controller to load a slave device. A transition low to high on CTL0 would latch the data on 32-bit bus into the slave conditioned by a minimum 5ns setup time.
My approach: I use GPIF II Designer for FX3, I/F type is “Master”, Communication type is “Asynchronous”, 32-bit bus, one single control “CTL0”, CTL0 is “Early” and “Toggle”, initially 1 (high).
State machine states: START, IDLE, DATA_CTRL, REMOVE_DATA
In DATA_CTRL “Repeat Count is 1”, Repeat actions until next transition, DR_DATA, DR_GPIO (CTL0). This state (in my opinion and intentions) should last exactly 2 clocks and because CTL0 is “toggle” and initialized to “high”, the first clock CTL0 will be driven low and the second clock will be high, so I generate the low to high transition that will latch DATA on 32 bits into the slave.
In DR_DATA I have “Update new value from data source” checked, data source is “Socket”, Thread number is “Thread0”, and “Remove data from data source” is NOT checked.
In state REMOVE_DATA all user i/f is disabled with the exception of “Remove data from data source”. Of course, I have a DR_DATA action added in this state. My intention here is just to remove source data used in previous state. I expect here to have CTL0 stay untouched (left “HIGH” from the previous state) and after this action state machine should point to next unused data word.
I read all the possible documents but because things don’t work and I have not the optimal electronic means to check, I need advise and/or assurance from somebody more experienced and knowledgeable on the above.
Thank you in advance for your help.
PS. Another question: If in a DR_DATA of a state I have “Remove data from data source” NOT checked, can I combine it with a next state where I have “Update new value from data source” checked and “Remove data from data source” checked and can I be sure that in these 2 states one single data word is actually addressed until removal?
Update new value from data source -This option updates the data bus with the data word present in the Source and removes the word from the specified Source.
Remove Data from the Data Source:When this option is disabled data source continue to point to same data
DR_DATA has two internal stages:update_bus and pop_data. The update_bus updates the data bus with the word present in the Source and happens as soon as the state machine enters the particular state. The hardware state machine works using the interface clock (in synchronous protocols) or the FX3 internal clock (in Asynchronous protocol). Every clock cycle, the update_bus happens irrespective of "Repeat actions until next transition" option in the state setting. Pop_data removes the data word from the Source and happens once or multiple times depending on the "Repeat actions until next transition" option in the state setting
I see that you have mentioned that it does not work properly. Can you provide more detail on the error? Do you think that the issue can be recreated just by using FX3 kit? If so, please provide your firmware and the GPIF project. If so, we can test it here and let you know more
Thank you very much for your reply.
I am trying to configure an FPGA on 32 bits. I know that some words are received by the fpga correctly, so no line is stuck high or low or some lines are cross-shorted. But at the end of MB of data CRC is not verified by the fpga. I will have to implement some "read" probably, but I will appreciate your help for what I need to make sure at this point it has to be correct.
The attached GPIF II project shows my intention. I set 32-bits on the bus (one clock to generate setup time), then in the next state I assert CLK high (to strobe data into the fpga) while keeping data exactly as in the previous state. I used the UI as understood to do this, but please check on my settings. So, state DATA_CFG takes one internal clock (asynchronous mode) and state CFG_STRB another clock. During both states we drive the data bus with the same word. Data gets renewed at the beginning of DATA_CFG.
I tried to lower the PIB clock frequency, I tried all the drive strengths possible. I do not have a means to check data validity for all data sent by host. Firmware cannot apply to FX3 DVK. I have an auto-mode GPIF II. My case is not like a big bug exists. More like I have a signal integrity issue. But it does not respond to frequency and drive strength. I had a "manual" GPIF variant and verified that before sending to GPIF data in the internal buffers were as expected (basically).
Please see the attached GPIF II project. Thank you.