I would like to customize Slave FIFO project by adding a input control pin.
Is it possible to initiate data transmission through GPIF from external device to the End-point when the rising-edge on one of the GPIF pins is appeared? Besides I need to transmit a strictly defined amount of data (probably I need to use counter in GPIF designer) and then I want to go back to waiting for the rising-edge state.
Which pin of GPIF for such input I should use?
You can have a look at AN65074 application note and the example firmware. The example demonstrates a master slave communication where the FPGA is a master and FX3 a slave. http://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inter...
The FPGA commands the FX3 (to read and write data). I suppose this meets your requirement where you want another device to start data transfer on FX3 GPIF. Here the flow control is implemented using the Flags in the FX3. You will have to make sure that the USB host is actually reading the data when the FPGA writes, else the FX3 buffers will get filled and the flag will prevent any further transfer from the FPGA. You can use the same example to understand the implementation. If you want a fixed amount of data transfer, you can actually use counter in the GPIF state machine. Counter based implementation we have shown in AN75779 (although it is a image sensor application, but you can understand how to implement a GPIF project where you rely on counting the data. Please ket us know if you have any questions.