Fx3 Write transfer

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MaMa_4520856
Level 4
Level 4
25 replies posted 25 sign-ins 10 replies posted

Hello,

When I'm trying to write data to Fx3 device from a FPGA device, I always get zero-lengh data transfer despite buffer being full (I know it is full base on the state of DMA flags). I noticed strange behavior of my RDY signal in a middle of a transfer it goes low for some reason and after few clock cycles it goes high (as it should be)

MaMa_4520856_0-1620404894026.png

 

 

 

 

 

 

 

In attachment i'm sending you firmware which I use and state machine from GPIF designer

regards,

Mateusz

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Hello Mateusz,

Thank you for confirming that you are using the AUTO DMA channel in the firmware.

From the firmware, I noticed that DMA buffer size used is 1024 as LOOPBACK_SHRT_ZLP is enabled. And the DATA counter value set in the GPIF state machine is 256 (0-255) which will read 256 * 2 (16bits) = 512 bytes of data.

So, once the 512 bytes of data is read by the GPIF (i.e. DATA_CNT_HIT will be triggered), the RDY signal will be  deasserted. If the RDY signal is expected to be HIGH for whole transfer i.e. 1024 bytes writing to FX3, then LD_DATA_COUNT should be set 511 instead of 255

LD_DATA_COUNT.PNG

DATA_COUNT_HIT.png 

 

Please let me know if further queries on this

Regards,
Rashi

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