cancel
Showing results for 
Search instead for 
Did you mean: 

USB Superspeed Peripherals

MaAr_2545856
New Contributor II

The FX3 first configures the FPGA using SPI lines and then again IO matrix is reconfigured for the 32-bit interface. The FX3 has to stream a video of resolution 962*766 @ 60FPS. I have modified the design as per the 32-bit interface. 

I added the function

CyU3PGpioDeInit();

CyU3PSpiDeInit();

New IO matrix for 32bit interface

After FPGA configuration. FPGA got programmed successfully but I am not able to stream the image. The log message shows “Error in CyU3PDmaMultiChannelCommitBuffer: code 71”

Then I modified as per

"Invalid Sequence Error in Multi-Channel Commit Buffer - KBA218830"

After that, I am getting the same error. I have attached the code for your reference.

0 Likes
1 Solution
Hemanth
Moderator
Moderator

Hi,

In main function:

CyU3PDeviceCacheControl(CyTrue, CyTrue, CyTrue); needs to be changed to CyU3PDeviceCacheControl(CyTrue, CyFalse, CyFalse);

Regards,

Hemanth

Hemanth

View solution in original post

0 Likes
8 Replies
Hemanth
Moderator
Moderator

Hi,

Commit Buffer failure shows that the rate at which the DMA buffers are getting filled is more than the rate at which they are consumed on the USB side.

Can you try decreasing the Horizontal Blanking time? (Idea is to decrease the rate of filling of DMA buffers)

Regards,

Hemanth

Hemanth
0 Likes
MaAr_2545856
New Contributor II

As I mentioned earlier, the Cypress example application works fine for the same FPGA configuration and bitstream. I am not able to get the output for ztex application firmware ( FPGA programming + FX3 UVC  example firmware).

0 Likes
MaAr_2545856
New Contributor II

Is there any update from your side?

Do I have to send the hardware for testing?

0 Likes
Hemanth
Moderator
Moderator

Hi,

We should know what is the status of the firmware and where is it getting stuck (if it is).

Using the message logging APIs - ztex_log, I don't think you can get logs continuously in your Host Application. Am I correct?

I see that when you call CyFxSwitchtoslFifo(), you disable SPI, enable 32 bit GPIF and make the lpp Mode as CY_U3P_IO_MATRIX_LPP_DEFAULT.

So, from here you can use UART block (since SPI is not being).

Referring to AN75779 firmware: Please have a look at CyFxUVCApplnDebugInit().

Can you do the same in your application?

After which you can get the UART log(by using CyU3PDebugPrint) on GPIO_55 of FX3.

After implementing the above, you can use a UART-USB bridge to see the logs on UART terminals like TeraTerm.

Regards,

Hemanth

Hemanth
0 Likes
MaAr_2545856
New Contributor II

we can see the log message using ztex_log continuously.

I cant use UART block because in my hardware those pins are not exposed. The only way to debug is using ztex_log API. when I debugged I am getting this error.

“Error in CyU3PDmaMultiChannelCommitBuffer: code 71”

0 Likes
Hemanth
Moderator
Moderator

Hi,

- Please check after how many prod events(i.e after committing how many full buffers) are you running into CommitBufferFailure.

- When you mentioned - "the Cypress example application works fine for the same FPGA configuration and bitstream", did you test it by loading AN75779 firmware on your board? (I know that it was verified before - by connecting your FPGA output to FX3 Explorer kit where the transfers were good.)

- I have seen that the buffer size you are currently using is 30KB. You can try increasing the buffer size and test. You have to make sure that the buffer size allocation does not exceed the maximum allowed(Channel creation fails otherwise in runtime).

As an example I am attaching cyfxtx.c file and fx3.ld file which has the following memory structure:

code area = 160KB

DMA Buffer area = 300KB

If your code size is larger than 160KB then you need to change these files accordingly to adjust the same. 

Regards,

Hemanth

Hemanth
0 Likes
MaAr_2545856
New Contributor II

My img size is 178KB.

I have changed the

/* UVC Video Streaming Endpoint Packet Count */

#define CY_FX_EP_BULK_VIDEO_PKTS_COUNT  (0x20)

This is the one I am using.

#define CY_U3P_MEM_HEAP_BASE         (0x40038000 + 0x800)

#define CY_U3P_MEM_HEAP_SIZE         (0x8000)

/*

   The last 32 KB of RAM is reserved for 2-stage boot operation. This value can be

   changed to 0x40080000 if 2-stage boot is not used by the application.

#define CY_U3P_SYS_MEM_TOP           (0x40080000)

I am not getting the output.

0 Likes
Hemanth
Moderator
Moderator

Hi,

In main function:

CyU3PDeviceCacheControl(CyTrue, CyTrue, CyTrue); needs to be changed to CyU3PDeviceCacheControl(CyTrue, CyFalse, CyFalse);

Regards,

Hemanth

Hemanth

View solution in original post

0 Likes