FX3 watermark on WR access

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JaRo_4664191
Level 2
Level 2
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Hi,

I'm trying to use the watermarks to end the GPIF2 data transfers.

My FX3 design is a 32b slave FIFO with flagA as ready/empty and flagB as watermark (both thread dependent). When accessing the FX3 in RD mode (U2P), the watermark is working as expected and everything goes great.

When accessing in WR mode (P2U), for some reason, the watermark comes earlier than what I would expect. I'm sending a whole FX3 buffer (16KB) from my FPGA and counting the amount of data sent (in 32b words), so for now the watermark flag it is not at the FPGA side.

The watermark for P2U access is configured with a value of 6, so, according to the documentation, the flag should go down when there are 2 samples left to be sent. At the FPGA I'm double registering the watermark, so I'm expecting the watermark to become low when there is no more data to be sent. However I still see that, even after the 2 cycle delay, the watermark does not arrive where I am expecting it. 

I'm including the chip scope capture so you can have a look, as well.

Screenshot 2021-02-22 at 22.13.23.png

The configuration for the FX3 watermark is as follows:

Screenshot 2021-02-22 at 22.15.01.png

 Thanks in advance.

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1 Solution

Hello,

Actually it should be at 4093th

>> In the  burst mode trace, the flag B (00) is seen on the 4094th edge (i.e. the edge at which cursor is placed), so the actual FLGA B pin would have been driven low by FX3 at 4092 clock edge. 

Two words of data need to be written after the clock edge at which Flag B is sample LOW. So, if the actual flag B is going low at 4093th clock edge then only one data word is written (i.e. at 4094 th clock edge) as at 4095 the clock edge the SLWR is de asserted

To know if the data is over sampled at some point or if the problem is from the watermark side. Please follow the watermark flag and stop the data transfers accordingly. The DMA buffer on FX3 will be full and committed to USB. Please check the data received by USB using Control center. Based on the data read we can know if the data sent and received are same. If not, there might be some problem in timings of Slave FIFO write.

As multiple threads for reads and writes are used in your design unlike default AN65974, please let me know if the custom GPIF state machine can be shared.

Regards,
Rashi

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