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USB Superspeed Peripherals

poas_4520791
New Contributor II

Hi,

i want to transfer some bytes of data from FX3 to DDR3.For that my application is

FX3        ----->        FX3       ------>      FPGA

(U-Port)               (P-Port)   GPIF ii      

I am using Slavefifosync firmware and modified to meet my application.I am able to transfer data from U-Port to  P-Port of FX3.

My question is how to transfer data from P-Port of FX3 to FPGA(Zynq side).

Regards,

Aswini.

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1 Solution
JayakrishnaT_76
Moderator
Moderator

Hello Aswini,

Please refer to section 5.1 and 5.2 of the Application Note AN65974. The link to the application note is given below:

https://www.cypress.com/file/136056/download

For successful read operation from the FIFO, you should make sure that the timing diagram mentioned in section 5.1 is followed strictly. The FPGA should implement this. Also, please refer to table 3 to understand the different timings mentioned in section 5.1.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna

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17 Replies
JayakrishnaT_76
Moderator
Moderator

Hello Aswini,

Please refer to section 5.1 and 5.2 of the Application Note AN65974. The link to the application note is given below:

https://www.cypress.com/file/136056/download

For successful read operation from the FIFO, you should make sure that the timing diagram mentioned in section 5.1 is followed strictly. The FPGA should implement this. Also, please refer to table 3 to understand the different timings mentioned in section 5.1.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna

View solution in original post

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poas_4520791
New Contributor II

Hello,

Can you  explain how to draw state machine in GPIF II designer tool for transfering data from FX3 to DDR3.

Regards,

Aswini

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JayakrishnaT_76
Moderator
Moderator

Hello,

For learning and understanding how to use GPIF II designer for developing any state machine, please refer to GPIF II quick start and user guide which are provided along with FX3 SDK. This can be found in the following location.

C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\GPIFII_Designer

Note: The path can change depending on the location where you installed the SDK.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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poas_4520791
New Contributor II

Hello,

I'm new to this GPIF II designer tool  and I have red the pdf's which you suggested me to read.I just created the states, after that what actions i should select in a particular state and how  the transitions equations are taking that i'm not getting.Can you please let me know about this.

Regards,

Aswini

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JayakrishnaT_76
Moderator
Moderator

Hello Aswini,

The GPIF II state machine consists of a given number of states as a normal state machine. Each state can be programmed to perform a given action. This action can be performed either once or can be repeated a number of times until a state transition occurs. The actions that are supported by the GPIF II state machine is listed in section 4.3 of the document gpif2_designer_userguide.

The transition from one state to another depends on the transition equations. The different transition equations supported by GPIF II state machine can be found in section 4.4 of gpif2_designer_userguide.

Please go through the above sections to understand about the supported actions and transition equations. Once you understand this, you need to develop your own state machine depending on your application. The actions and the transition equations are completely based on your application. This state machine which you develop using GPIF II designer is for the slave device(FX3). I understand that your application is just to read data from the FIFO. In this case, you can make use of the state machine that is provided along with the Application Note AN65974. The link for downloading the complete file is given below:

https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inte...

Download AN65974.zip from this link. This has the complete firmware and the GPIFII files for implementing the slave FIFO application. Please read AN65974 document completely to understand the entire application. Then use this as a reference to develop your application.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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poas_4520791
New Contributor II

Hello,

I have modified GPIF  state machine and interface settings based on AN65974 GPIF II files, and now FLAG C is getting '0' and reamining flags are high.FLAG C (active low-0),so i'm having data in the dma buffers,but im not able to receive the data in FPGA side.

what may be the issue.Kindly,let me know the issue.

Regards,

Aswini

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JayakrishnaT_76
Moderator
Moderator

Hello,

Please let me know whether you are using the firmware and GPIF II state machine provided in AN65974 itself or not.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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poas_4520791
New Contributor II

Hello,

I'm using the AN65974 firmware and GPIF II state machine only.

Regards,

Aswini

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JayakrishnaT_76
Moderator
Moderator

Hello,

If you are using the AN65974 firmware and GPIF state II machine, then the initial value of the flag C will be 0. This is expected. This means that the FIFO is empty. So you cannot read data from the FIFO as there is no data in the FIFO.

For making it not empty, please send some data through U Port. This can be done by using Control Center. After a successful transfer of data takes place, you can see that the flag C will go high. During this time, FPGA should read data from the FIFO.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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poas_4520791
New Contributor II

Hello,

I'm sending the data through control center but i'm not getting that data in FPGA side.

I have one doubt "the initial value of the flag C will be 0. This is expected. This means that the FIFO is empty. So you cannot read data from the FIFO as there is no data in the FIFO".

      The flags are active low ,so if a flag is 0 then it means the buffer is  having some data .Initially flag C is 1(low) after programming i'm getting flag C as 0(high) and ,here flag D (watermark flag) is 1(low ) before and after programming also.If flag D is 0(high) it will terminate the transaction.It seems everything is fine upto GPIF II but why the data is not not reaching FPGA?

Please let me know  what is the issue.

Regards,

Aswini

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JayakrishnaT_76
Moderator
Moderator

Hello Aswini,

Please refer to Fig. 3 of the application note AN65974. This is the timings that are to be met for the read operation. You can see the flags in this figure.It is mentioned that 1 = not empty and 0 = empty. So if a flag is low it means that the FIFO is empty for read operation.

While the start of the transfer, you need to monitor the ready flag. This is because the watermark flag shows a different behaviour at the start of the transfer. Watermark flag is used for ending the transfer. For more clarity on this, please refer to the following thread:

DMA flags Basic doubt

I find that the flags are asserted properly in your case. Are you issuing a read signal from the FPGA and following the timings exactly as mentioned in fig3 of AN65974?

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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poas_4520791
New Contributor II

Hello,

I'm not getting the same timings as in fig3 of AN65974 in FPGA side and after programming  i'm getting the constant values .The values be like

SLCS-0

flagC-0

and reamining are 1.

In the U to P Callback function ,i'm receving the data in buffer then what may be the reason for not transferring the data ,is it the problem with GPIF II?

Regards,

Aswini

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JayakrishnaT_76
Moderator
Moderator

Hello,

You need to assert the signals as that mentioned in fig 3 of AN65974 from the FPGA side for reading from the FIFO and not from the GPIF II side. FPGA can make use of flags from the GPIF II side so as to assert these signals. The remaining are to be done from the FPGA side itself. Please check the implementation on the FPGA side.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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poas_4520791
New Contributor II

Hello,

It may be a minor doubt from your previous reply "I find that the flags are asserted properly in your case. Are you issuing a read signal from the FPGA and following the timings exactly as mentioned in fig3 of AN65974?".

Can you explain how to issue a SLRD signal /assert SLRD and SLOE signals from FPGA side.

Regards,

Aswini

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JayakrishnaT_76
Moderator
Moderator

Hello,

Please refer to section 11.4 of AN65974. This describes the implementation on FPGA side.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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poas_4520791
New Contributor II

Hello,

The signals are asserting correctly from FPGA  and flags are working fine,but the data is initially ffff and after programming FX3 it is changing to 0000 as shown below.

ila probes.PNG

what should be done to get the data from FX3 to FPGA. Kindly let me know.

Regards,

Aswini

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JayakrishnaT_76
Moderator
Moderator

Hello,

Please confirm that the address lines asserted by the FPGA is correct. Please go through the following thread which addresses problem as yours.

Re: fx3 application

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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