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USB Superspeed Peripherals

MaXi_1246331
Contributor

The datasheet of FX3 says for synchronous slave FIFO read, the data becomes valid in tco after the rising edge PCLK (from FPGA to FX3). I find the data becomes valid in tco after the falling edge PCLK, I draw this conclusion from 2 sources. 1) The captured FPGA internal signal

2) The PCLK and data signal captured at the PCB, from FPGA to FX3, as follows. The blue signal is the least significant data bit.

I guess FX3 devices may be updated and the document may not be updated, leading to the difference between description and actual behavior of the devices. Is my understanding correct?

20200705232752.jpg

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1 Solution
YashwantK_46
Moderator
Moderator

Hello,


This seems to be causing the issue that you are seeing on your end.

The default slaveFifo Sync state machine comes with a Positive Active Clock edge.

Also, you would need to make sure the FPGA follows the positive clock edge and all other parameters accordingly.

Please change this and build the project to get the cyfxgpif2config.h file.
Replace the old gpif2config.h file in your workspace with the newly generated config.h file and clean build the project again.

Please try with the latest image with Active Clock Edge: Positive and see if you get the expected results.

PS: For your reference, I have added the modified cyfxgpif2config.h file with Positive Active Clock edge. You can replace the old file with the one attached to this interaction.

Regards,
Yashwant

View solution in original post

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YashwantK_46
Moderator
Moderator

Hello,

As mentioned in the Section 5.2 Synchronous SlaveFIFO Read Sequence:

"The FIFO pointer is updated on the rising edge of the PCLK while SLRD# is asserted. This action starts the propagation of data from the newly addressed FIFO to the data bus. After a propagation delay of tCO (measured from the rising edge of PCLK), the new data value is present."

Even though the data is available at the falling edge, the data is only sampled on the rising edge of the PCLK in FX3 since the FIFO pointer pointing to the new data would be updated on the rising edge of PCLK.

Regards,
Yashwant

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MaXi_1246331
Contributor

For synchronous slave fifo read, the data is valid in Tco after the falling edge of PCLK. As we can see from the figure. The period of.PCLK is 200ns,I set PCLK very low as 5MHz to have a clear view of whether the data is valid after the falling edge or the rising edge. Note that tco is 7ns MAX according to datasheet. If the data is valid after tco of the rising edge of PCLK, the tco would be larger than 100ns, because the half period is 100ns. So, the data is NOT valid in tco after the rising edge of PCLK, but rather the falling edge of PCLK.

Is my understanding correct?

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YashwantK_46
Moderator
Moderator

Hello,

There is a 2 cycle latency from the point of the assertion of SLRD to the point of data being read by the master provided all the interface timing parameters are met properly.

Also, can you please elaborate on what you meant by, " The blue signal is the least significant data bit."?
Does this mean that you are using GPIF as a serial interface?

Please refer to the app note AN87216 which explains the interface parameters that the master needs to follow as well as the sequence.
The link for AN87216: https://www.cypress.com/file/124206/download 

Please make sure the interface timings on the master side are being met correctly and as mentioned in the above app note.

Regards,
Yashwant

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MaXi_1246331
Contributor

" The blue signal is the least significant data bit."

I mean the blue signal is D0 of the slave FIFO data bus.

I understand the 2 clock lantency, the it can not explane why I observe the data change after about 5 ns after the falling edge of CCLK.

I hope you can explain the difference between my obervation and the datasheet.

Thank you

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YashwantK_46
Moderator
Moderator

Hello,

Can you please let me know if you have made any changes to the SlaveFifoSync example that you are trying out?
If you are using some other firmware, please let me know.

Can you please let me know if the active clock in the GPIF designer is set to positive or negative?

Regards,

Yashwant

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MaXi_1246331
Contributor

IMG_20200720_162533.jpg

I observe the active edge is negtive. Which document explain that I can change the active edge?

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YashwantK_46
Moderator
Moderator

Hello,


This seems to be causing the issue that you are seeing on your end.

The default slaveFifo Sync state machine comes with a Positive Active Clock edge.

Also, you would need to make sure the FPGA follows the positive clock edge and all other parameters accordingly.

Please change this and build the project to get the cyfxgpif2config.h file.
Replace the old gpif2config.h file in your workspace with the newly generated config.h file and clean build the project again.

Please try with the latest image with Active Clock Edge: Positive and see if you get the expected results.

PS: For your reference, I have added the modified cyfxgpif2config.h file with Positive Active Clock edge. You can replace the old file with the one attached to this interaction.

Regards,
Yashwant

View solution in original post

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MaXi_1246331
Contributor

Thank you. This problem is solved.

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