FX3 state machine behavior

james4870291 · ‎Apr 16, 2021

Dear Sirs,

Attached is part of my FX3 state machine when doing READing Data and the interface timing I suppose FX3 would be.

State machine will go from READ state to RD_WAIT state triggered by rfifo_empty(from external device:FPGA).

my question is :

If I just want to read 4 times, but state machine will go to RD_WAIT(slcs/slrd/sloe==HIGH) after it samples rfifo_empty==HIGH at positive edge of PCLK. If the interface timing is like what I draw, there will exist 5 read transfers.

How to avoid this situation? (Or maybe my assumption about interface timing is not correct)

Best regards,

james

Rashi_Vatsa · ‎Apr 16, 2021

Hello James,

As per the state machine and the timing sequence, the state machine will transition to RD_wait when rfifo_empty goes high. rfifo_empty in the timing sequence goes high after fourth clock edge which means the data will be read (IN_DATA) for 4 clock edge and then state machine will transition to RD_WAIT state.

Please let me know if FPGA drives SLRD, SLOE,SLCS signals or by FX3. The data will be read when in READ state as IN_DATA action is called in READ state. Once the state machine transitions to READ_WAIT, no actions are called in the state so the data will not be sampled on the fifth clock edge

Regards,
Rashi

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FX3 state machine behavior

FX3 state machine behavior

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