cancel
Showing results for 
Search instead for 
Did you mean: 

USB Superspeed Peripherals

james4870291
New Contributor II

Dear Sirs,

Attached is part of my FX3 state machine when doing READing Data and the interface timing I suppose FX3 would be.

State machine will go from READ state to RD_WAIT state triggered by rfifo_empty(from external device:FPGA).

my question is :

If I just want to read 4 times, but state machine will go to RD_WAIT(slcs/slrd/sloe==HIGH) after it samples rfifo_empty==HIGH at positive edge of PCLK. If the interface timing is like what I draw, there will exist 5 read transfers.

How to avoid this situation? (Or maybe my assumption about interface timing is not correct)

read_state_machine.JPG

 

Best regards,

james

0 Likes
1 Solution
Rashi_Vatsa
Moderator
Moderator

Hello James,

As per the state machine and the timing sequence, the state machine will transition to RD_wait when rfifo_empty goes high. rfifo_empty in the timing sequence goes high after fourth clock edge which means the data will be read (IN_DATA) for 4 clock edge and then state machine will transition to RD_WAIT state. 

Please let me know if FPGA  drives SLRD, SLOE,SLCS signals or by FX3. The data will be read when in READ state as IN_DATA action is called in READ state. Once the state machine transitions to READ_WAIT, no actions are called in the state so the data will not be sampled on the fifth clock edge

Regards,
Rashi

View solution in original post

0 Likes
3 Replies
Rashi_Vatsa
Moderator
Moderator

Hello James,

As per the state machine and the timing sequence, the state machine will transition to RD_wait when rfifo_empty goes high. rfifo_empty in the timing sequence goes high after fourth clock edge which means the data will be read (IN_DATA) for 4 clock edge and then state machine will transition to RD_WAIT state. 

Please let me know if FPGA  drives SLRD, SLOE,SLCS signals or by FX3. The data will be read when in READ state as IN_DATA action is called in READ state. Once the state machine transitions to READ_WAIT, no actions are called in the state so the data will not be sampled on the fifth clock edge

Regards,
Rashi

View solution in original post

0 Likes
james4870291
New Contributor II

Dear Rashi,

In my application, FX3 is Master(drive SLRD, SLOE,SLCS signals). And rfifo_empty is driven by FPGA to inform FX3 there is no data valid for READ.

 

As my understanding, it seems that FX3 must sample rfifo_empty=1 at the fifth clock edge, and pull SLCS and SLRD to HIGH (enter RD_WAIT state). At this situation, FPGA side will see the fifth read action, am I right ?

 

Thanks a lot,

james

0 Likes
Rashi_Vatsa
Moderator
Moderator

Hello James,

Your understanding it correct.  DR_GPIO settings has delayed option. Please confirm if the "early" option is marked

Please let me know if every time data is to be read only for 4 clock cycles. In that case the repeat count of the state setting can be set to 4.

Regards,
Rashi
0 Likes