FX3 slavefifo mode -SynchronousSlave FIFO Write Sequence question

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Anonymous
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Hi,

   

I read the notebook of AN65974.pdf. when i read the part of Synchronous Write Cycle Timing on page of 9 and 10, i find that "3cycle latency from SLWR#to FLAG" on the timing. But i cann't understand the meaning of the latency?  anyone could help me?

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Anonymous
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The Flag is updated 3 cycles after the FIFO is gone full. So you have to monitor a partial full flag in order to lose no data.

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Anonymous
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Chris R, thanks for your help! 

   

In your meaning, I can only use the paritial full flag  but not the full flag in the synchronous slave fifo mode?

   

 

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Anonymous
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 chris.R can you tell me more details about the partril flag configuration?

   

 thank you !

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