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USB Superspeed Peripherals

New Contributor

Hi,

I am studying the slave FIFO interface for my application. Probably, I will use sync. slave FIFO interface 2 bit mode. I have a few questions as below:

1. Is it possible to set the max. transfer size of the USB endpoint and the DMA buffer size to 16KB?

2. What is the max. DMA buffer size? is it 224KB?

   The default memory map used for FX3 applications is as follows:

   Descriptor area    Base: 0x40000000 Size: 12KB

   Code area          Base: 0x40003000 Size: 180KB

   Data area          Base: 0x40030000 Size: 32KB

   Driver heap        Base: 0x40038000 Size: 32KB  (Update cyfxtx.c to change this.)

   Buffer area        Base: 0x40040000 Size: 224KB (Update cyfxtx.c to change this.)

   2-stage boot area  Base: 0x40078000 Size: 32KB  (Update cyfxtx.c to change this.)

3. I want to know more about the behavior of the FLAGx signal.

a) For example, the USB endpoint size and DMA buffer size is 4KB, the USB host sends 1KB data to the FX3. Does the FLAG go low after the entire 1KB data committed to the consumer port? Or the FLAG goes low immediately after the data arrived the DMA buffer?

b) While the FPGA is reading the data out, there are new data coming from USB host to the DMA buffer. Will the unread data be corrupted (over-written by the new data)? Or, the FX3 will NACK the USB host?

Thanks,

Jason

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Moderator
Moderator

Hello Jason,

1. Yes, you can use the maximum endpoint size of the USB endpoint (say 1024 bytes in case of bulk endpoint) and use the buffer size as 16kB.

2. Yes, the maximum DMA buffer size allotted in case of CYUSB3014 part is 224kB. This buffer area can be split into multiple buffers corresponding to a single DMA channel.

3.(a) Please explain how you would like to configure the flag 'FLAGB' and what is the mode of DMA channel (AUTO/MANUAL).

   (b) In case you are using only buffer for the DMA channel, when the FPGA is reading data out from the buffer, the FX3 will NAK the new data coming from the host. In case you are configuring the DMA channel for multiple buffers (recommended), FPGA can read data and USB can send new data simultaneously.

Best regards,

Srinath S

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12 Replies
Moderator
Moderator

Hello Jason,

1. Yes, you can use the maximum endpoint size of the USB endpoint (say 1024 bytes in case of bulk endpoint) and use the buffer size as 16kB.

2. Yes, the maximum DMA buffer size allotted in case of CYUSB3014 part is 224kB. This buffer area can be split into multiple buffers corresponding to a single DMA channel.

3.(a) Please explain how you would like to configure the flag 'FLAGB' and what is the mode of DMA channel (AUTO/MANUAL).

   (b) In case you are using only buffer for the DMA channel, when the FPGA is reading data out from the buffer, the FX3 will NAK the new data coming from the host. In case you are configuring the DMA channel for multiple buffers (recommended), FPGA can read data and USB can send new data simultaneously.

Best regards,

Srinath S

View solution in original post

New Contributor

Hello Srinath S,

Thank you for your answer. I would like to have the following setup:

             USB Host                              FX3                                                  

                                                            (Consumer) Socket 0       GPIF                                                           

(Bulk-OUT Endpoint: 1KB)   >>>>      DMA buffer size: 1KB   <======>  FPGA  
                                                            DMA buffer count: 2                                                                     Using auto DMA

The application only transfers data from USB host to the FPGA. I consider to set the FLAG to indicate Empty/Not empty. So, my questions are:

1. when no data inside all the DMA buffers, the FLAG should be high (Empty)???

2. Once the USB send data to the FX3 with size <= 1KB. Then the DMA buffer 0 should fill with data and causes the FLAG assert (goes low) to indicate Not empty ?? Or, I need to make the FLAG assert in firmware?

3. Continue from Q2, if the master does not read that data out from DMA buffer 0, and the USB host writes another 1KB data to the FX3. Then, the DMA buffer 1 will fill the new data. When the master starts reading the data, the return data should be in sequence?? I mean first the DMA buffer 0 data and then the DMA buffer 1 data. If my understanding is correct, the DMA descriptor manages the sequence of the incoming data?

4. If the USB host sends only a few bytes data to FX3, then the DMA buffer 0 fills with these few bytes data. And then when the next USB transfer comes, the new data will save to the DMA buffer 1?

5. For this application, in fact the address pin is meaningless? Or, I still need to keep A[0] and keep it low?

Thanks,

Jason

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Moderator
Moderator

Hello Jason,

1. The FLAG can be configured as either

Current_Thread_DMA_Ready/Thread_0_DMA_Ready/Thread_1_DMA_Ready/Thread_2_DMA_Ready/Thread_3_DMA_Ready (or)

Current_thread_DMA_watermark/Thread_0_DMA_watermark/Thread_1_DMA_watermark/Thread_2_DMA_watermark/Thread_3_DMA_watermark.

I assume that you are using the Current_Thread_DMA_Ready flag.

The current thread is identified by the address driven on the FX3 A1:A0 pins by the FPGA. When the socket corresponding to the active thread has no data present in it, the FLAG gets asserted indicating that the buffer is empty. When data has been loaded into the buffer and is... gets de-asserted  indicating the FPGA that it can read the data from FX3. It has to be noted that t...

2. FLAG assertion is done once the buffer gets full or empty and need not be implemented in the firmware. The GPIO has to be configured as the flag pin from the GPIF II designer.

3. The sequencing of data transfers will be handled by the DMA fabric.

4. When the host writes a short packet, i.e lesser number of bytes, that particular gets committed and the new data that follows will be written onto the next buffer.

5. The A[1:0] pins need to be driven to select the thread associated with the socket that is used in you application. In case you do not wish the address lines, the thread can be selected in the GPIF II designer states as it is implemented in the AN75779 example application note.

Best regards,

Srinath S

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New Contributor

Hello Srinath S,

Thanks for your quick reply.

1. If there is only 1 socket in my application. Then, PIB_SOCKET_0 should be connected to GPIF Thread 0. So, can I just set the FLAG as Thread_0_DMA_Ready?

According to your answer, if I set to use AUTO DMA then the action "commit buffer" should be done automatically? And, the last statement, I have a bit confuse. Do you mean the FLAGA get de-asserted if there is only one buffer which is ready to be transmitted to the FPGA?

"the FLAG gets asserted indicating that the buffer is empty. When data has been loaded into the buffer and is... gets de-asserted indicating the FPGA that it can read the data from FX3. It has to be noted that th...

4. Will the FLAGA get de-asserted if the host writes a short packet?

"When the host writes a short packet, i.e lesser number of bytes, that particular gets committed and the new data that follows will be written onto the next buffer."

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Moderator
Moderator

Hello Jason,

>> Yes, you can set the FLAGA as Thread_0_DMA_Ready.

>> Whenever a buffer gets filled by the USB host and if it is committed to the GPIF II interface, then it means that the FPGA is ready to receive the data from FX3. This is indicated by the de-assertion of the FLAGA.

In case of a consumer endpoint,

FLAGA asserted -> indicates EMPTY and

FLAGA deasserted -> indicates NOT EMPTY.

>> The FX3 treats the short packet as one buffer of data and hence the FLAGA gets de-asserted on receiving a short packet too.

Best regards,

Srinath S

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New Contributor

Hi Srinath S,

Thank you for your explaination.

How can I know the DMA buffer is empty or full in the state machine (GPIF II designer tool)? Because I want to use it as a trigger to transit to next state.

Thanks,

Jason

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Moderator
Moderator

Hello Jason,

In the GPIF II designer, you can use the COUNT_DATA (or) COUNT_ADDR to keep track of the number of bytes filled in the buffer and to trigger an interrupt based on this value. The LD_DATA_COUNT (or) the LD_ADDR_COUNT can be used to load an initial value and the counter limit value. COUNT_DATA (or) COUNT_ADDR increments the value until the DATA_CNT_HIT (or) ADDR_CNT_HIT is reached and actions can be taken to switch to another state or to trigger an interrupt.

The value to be loaded in the counter limit value is obtained by the following formula.

Please refer to the AN75779 Application Note for reference implementation of the suggested method.

Best regards,

Srinath S

New Contributor

Hi Srinath S,

I setup the following environment:

- USB Bulk OUT endpoint with 1KB packet size

- DMA buffer: 8

- DMA buffer size: 1KB

USB Bulk OUT as producer and GPIF as consumer

#define CY_FX_EP_PRODUCER 0x01 /* EP 1 OUT */

#define CY_FX_EP_PRODUCER_SOCKET CY_U3P_UIB_SOCKET_PROD_1

#define CY_FX_GPIF_CONSUMER_SOCKET CY_U3P_PIB_SOCKET_0

/* Burst length in 1 KB packets. Only applicable to USB 3.0. */

#define CY_FX_EP_BURST_LENGTH           (1)

/* Size of DMA buffers used by the application. */

#define CY_FX_DMA_BUF_SIZE              (1024)

/* Number of DMA buffers to be used on the channel. */

#define CY_FX_DMA_BUF_COUNT             (8)

The GPIF interface and state machine:

FLAGA is set as Thread0_DMA_Ready

interface.jpgstate_machine.jpg

This idea is when the DMA buffer has data, then drive the SOP and then drive out all the data until the DMA buffer is empty. I use the Streamer tool to test. The USB transfer get failure after 8 commits (DMA MANUAL is used). It seems FX3 is unable to fill the data to the DMA buffer.

However, if I use USB control center and manually click Transfer-OUT 1KB, the USB transfer is fine (you can refer to the last picture). Do you have any idea?

pastedImage_16.pngconsole.jpgpastedImage_0.png

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Moderator
Moderator

Hello Jason,

The failure could be because Streamer application is writing data into the FX3 faster than it is being consumed by the GPIF II. Please let me know if the transfer stops after 8kB of data transfer when using the Streamer application. From the Streamer application screenshot, I find 14 successes whereas the UART log from the terminal shows only 8 packets of data transmitted. Kindly, confirm.

Best regards,

Srinath S

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New Contributor

Hi,

I will check on it. By the way,  is there any mistake regarding the DMA configuration or the USB endpoint setting?

Can I use !DMA_RDY_TH0 as trigger if the DMA buffer is not empty?

Thanks,

Jason

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Moderator
Moderator

Hello Jason,

- In your case, since you have used only one thread, current thread and thread 0 point to the same. So, !DMA_RDY_TH0 and !DMA_RDY_CT do not make a difference. But, since you have used DMA_RDY_TH0 as the flag to drive data, it would be meaningful to use the same to stop driving data.

- In case failures occur only with the Streamer application and not with the Control Center, then the issue is most likely that the USB interface is sending the data faster than the GPIF II interface. To avoid this, you can increase the data rate on the GPIF II interface or increase the Timeout Per Xfer on the Streamer application.

Please let me know the observations.

Best regards,

Srinath S

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