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Hi Everyone,
I have been trying to program the Slavefifo image file to FX3 RAM and Boot from USB in my Custom Cypress Device Board.
Initially it detects as Cypress Boot Loader and After i have programmed the Slavefifo_loopback image file by using USB Control Center, It shows that Programming Succeed.
After that it never enumerates and shows none of the USB device. Even in Hardware device Manager it never detects any new USB device?.
I have properly Configured the PMODE to Z11 as it for USB Boot.
Same thing i have tried with Cypress DVK Board, in its working perfectly. Its able to remunerate as loopback device.
I guess i have some issues in the Hardware, but couldn't get any hint what it is. Because i have designed the Board based on the Schematics of Cypress DVK.
Could somebody suggest what could be the cause for this issues?
Thanks in advance.
Rgds,
Muthu
Solved! Go to Solution.
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Hi Rashi,
Thanks for your input. I have found out the issue . its because RX & TX lines of USB3.0 where interchanged in adaptor board by mistake and it has been corrected out. Just found out by understanding that the booting was happening when i connected to USB 2.0 port in PC and where as it was not if i plugged to USB3.0
regards
Muthu
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Hi Muthukumar,
- I would like to know which cypress part number (example: cyusb3014) are you using in your custom board?
- Can you load bulksourcesink firmware (C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\basic_examples\cyfxbulksrcsink) and check whether you get the logs
- Also, can you share the schematics of the FX3 portion of the custom board?
Regards,
Rashi
Rashi
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Hi Rashi,
Thanks for your input. I have found out the issue . its because RX & TX lines of USB3.0 where interchanged in adaptor board by mistake and it has been corrected out. Just found out by understanding that the booting was happening when i connected to USB 2.0 port in PC and where as it was not if i plugged to USB3.0
regards
Muthu
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Hi Rashi,
I have another question. Now i'am working on FPGA part. Iam only reading from FX3 from FPGA. I have built a engine that will read single 16 bit data and reset the cycle. I look for FLAGC (its set as active low) and read only one 16bit data from data bus. (this has been validated by providing manual trigger to engine instead of FLAGC)
In real condition, after remuneration, FLAGC is always low, even if i write the data to FX3 from host through Cypress control centre tool.
fifo address i have set permanently A0==1; A1==1.
Firmware used is Sync Slavefifo Example.
is there a issue in sending only 2 byte data from cypress control centre?
I also have little confusion on Thread and socket handling for my above mentioned application? could you please clarify?