FX3 data lost during DMA transfer

[AlEr_4025481]

Hi there,

I'm fighting with data lost during DMA transfer and totally stuck on two questions... To be sure that received data is monotonic I attached an FPGA which works as a basic counter. FPGA sends to FX3 512 byte blocks, each block filled by 16-bit block number. For example, first 512 bytes of data filled by 0x0000, 2nd 512 bytes filled by 0x0001, 3rd 512 bytes filled by 0x0002 and so on. Verilog source code is below.

module main(
    input RD,
    input RST,
    output [15:0] DATA,
output LED
    );
reg [23:0] counter;
always @(negedge RST or posedge RD)
begin
if (!RST)
counter <= 0;
else
counter <= counter + 24'd1;
end
assign DATA = counter[23:8];
assign LED = counter[13];
endmodule

FX3 GPIF configured as master async device, each DATA_IN action asserts RD output.

DMA configuration:

    dmaCfg.size = 16384;
    dmaCfg.count = 1;
    dmaCfg.prodSckId = CY_U3P_PIB_SOCKET_0;
    dmaCfg.consSckId = CY_U3P_UIB_SOCKET_CONS_1;
    dmaCfg.dmaMode = CY_U3P_DMA_MODE_BYTE;
    dmaCfg.notification = 0;
    dmaCfg.cb = NULL;
    dmaCfg.prodHeader = 0;
    dmaCfg.prodFooter = 0;
    dmaCfg.consHeader = 0;
    dmaCfg.prodAvailCount = 0;

As soon as vendor code received data transfer starts with CyU3PGpifSMSwitch() API. Every tyme I'm trying to get exactly 16384 bytes of data through bulk IN EP, no less, no more, because GPIF SM uses LD_DATA_COUNT action and grabs only 8192 words (16384 bytes). But unfortunately sometimes I see a data lost in the MIDDLE of transfer. Sometimes data received correctly, sometimes not. And as I see when data lost happens, it's always happens at the same offset between 0x0008 and 0x0009 words as on the 3rd picture below.

So my first question is what I missed? Should I change something in GPIF or DMA config?