We are planning to develop custom board with cypress FX3 chip and FPGA. We are trying to implement FX3 synchronous slave fifo interface with FPGA.
1) In FX3 chip, what is the use of XTAL IN & OUT, CLKIN and CLKIN_32. It mentioned in document as “can be left unconnected if they are not used”. Anyways there is no “CLKOUT” pin in FX3 as FX2, so we can’t take outside to external FPGA.
2)In our design, we are using slave fifo interface and PCLK is driven form FPGA to FX3. Whether GPIF II slave fifo works on crystal clock or PCLK.? Also whether we can provide both clocks PCLK and Crystal clock to FX3.
The clock which runs all the FX3 can be supplied through any one of the following ways.
19.2 Mhz crystal on XTAL_IN, XTAL_OUT pins
19.2 Mhz clock on CLKIN pin
26 Mhz clock on CLKIN pin
38.4 Mhz clock on CLKIN pin
56 Mhz clock on CLKIN pin
Among the above 5 options any one can be used. If 19.2 Mhz crystals is connected on XTAL pins then CLKIN pin can be left unconnected. Also if any of the 4 clocks (frequencies mentoned above) is connected to CLKIN pin XTAL pins can be left unconnected. THE CLKIN32 pin is independednt of these and it is used to connect 32 KHz watchfdog timer used for wakeup from low power. If watchdog timer is not used in your application, this pin can be left unconnected.
By the way, the clock for Slavefifo interface is to be supplied by the FPGA on GPIO16 (PCLK) which is a separate pin. If FX3 is going to act as master then Clock will be supplied from this pin to the FPGA.,
- Madhu Sudhan
We have used FX2 synchronous slave FIFO interface previously, in that case we took "clkout" pin from FX2 and driven to FPGA. we used this "clkout" for stream in / stream out operations between FX2 and FPGA. "IFCLK" pin is left unconnected.
But in FX3 GPIF II synchronous slave fifo, we don't have "clkout"pin. According to the slave fifo document its mentioned "PCLK" as input to FX3 slave fifo.
Question 1: We are using 100Mhz interface clock (PCLK) its driven from FPGA to Fx3, whether this scheme is correct and can be used for stream IN / stream OUT operations in FX3 ? *Exactly reverse in Fx2, we have taken clk form Fx2 (clkout pin)
Question 2: We are using FX3 slave fifo mode, in this scheme FPGA will be master and initiating stream in/out transfers. Whether in this case also FX3 will supply clock on "PCLK" pin to FPGA? If its supplying then what would be the frequency and whether we can also drive it from FPGA to override it.