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USB Superspeed Peripherals

Tomek
New Contributor

Hi,

I want to transfer video data from FPGA to PC by using custom board  FX3- CYUSB2014. Output data from FPGA : 640x480, 30 fps, 90 MHz clock, YUY2 format, 8 bit data bus connected with  2.0 USB cable  to host PC. I edited AN75779 firmware but without success. I use VLC, USBVideoClassBulk works fine on my hardware. Is there anything am missing to change?

Tom

In  cyfxuvcdsr.c file

 

/* Standard High Speed Configuration Descriptor */

 

/* Class specific Uncompressed VS Frame descriptor */

        0x1E,                           /* Descriptor size */

        0x24,                           /* Descriptor type*/

        0x05,                           /* Subtype: uncompressed frame I/F */

        0x01,                           /* Frame Descriptor Index */

        0x01,                           /* Still image capture method 1 supported */

        0x80,0x02,             //z         /* Width in pixel: 640 VGA */

        0xE0,0x01,             //z         /* Height in pixel 480 VGA */

        0x00,0x00,0xCA,0x08,   //z         /* Min bit rate bits/s. 640x480x30x16

        0x00,0x00,0xCA,0x08,    //z        /* Max bit rate bits/s. Not specified, taken from MJPEG */

        0x00,0x60,0x09,0x00,    //z        /* Maximum video or still frame size in bytes(Deprecated) */

        0x15,0x16,0x05,0x00,      //z      /* Default Frame Interval 30 fps*/

        0x01,                           /* Frame interval(Frame Rate) types: Only one frame interval supported */

in uvc.c file

uint8_t glProbeCtrl20[CY_FX_UVC_MAX_PROBE_SETTING] = {

    0x00, 0x00,                 /* bmHint : no hit */

    0x01,                       /* Use 1st Video format index */

    0x01,                       /* Use 1st Video frame index */

    0x15,0x16,0x05,0x00, //z     /* Desired frame interval in the unit of 100ns: 30 fps */

    0x00, 0x00,                 /* Key frame rate in key frame/video frame units: only applicable

                                   to video streaming with adjustable compression parameters */

    0x00, 0x00,                 /* PFrame rate in PFrame / key frame units: only applicable to

                                   video streaming with adjustable compression parameters */

    0x00, 0x00,                 /* Compression quality control: only applicable to video streaming

                                   with adjustable compression parameters */

    0x00, 0x00,                 /* Window size for average bit rate: only applicable to video

                                   streaming with adjustable compression parameters */

    0x00, 0x00,                 /* Internal video streaming i/f latency in ms */

    0x00,0x60,0x09,0x00,   //z  /* Max video frame size in bytes */

    0x00, 0x40, 0x00, 0x00,      /* No. of bytes device can rx in single payload = 16 KB */

 

0x00,0x00,0x00,0x96,                 /* Max video frame size in bytes */

 

 

/* Configure the IO matrix for the device. */

    io_cfg.isDQ32Bit        = CyFalse;

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1 Solution
Tomek
New Contributor

Problem solved, i had problem on FPGA side. Thanks for your help.

Tom

View solution in original post

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3 Replies
JayakrishnaT_76
Moderator
Moderator

Hello,

Can you please confirm that the FPGA sends only 8 bits of data per PCLK to FX3? That is, to sample one pixel (16 bits), FX3 requires 2 clock cycles.

Please let us know if you have made any other modifications to default AN75779 apart from that mentioned in your description. Also, please calculate the size of the video frame in firmware and print the same in the infinite for loop. For calculating the size of the video frame, following steps can be used:

1. Declare a global variable to hold the size and initialize it to 0.

2. In the DMA callback function (CyFxUvcApplnDmaCallback), inside the CY_U3P_DMA_CB_PROD_EVENT, check if a full buffer or partial buffer is received. This check is already done in AN75779 by the following condition:

if (dmaBuffer.count == CY_FX_UVC_BUF_FULL_SIZE)

The above condition checks if the buffer is full or not. If it is not full, then it indicates that a partial buffer is received. Please note that the video frame should always end with a partial buffer.  

3. Use another global boolean variable and initialize it as false. 

4.  If the buffer received is a full buffer and the boolean variable holds false, then update the global variable for holding the frame size by adding it with dmaBuffer.count. That is,

global_var = global_var + dmaBuffer.count

5. If the buffer received is a partial buffer and boolean variable is false, then update the global variable for storing the frame size as mentioned above. In addition to this, set the boolean variable to true.

6. In the infinite for loop, check if the global variable is true. If it is true, then print the value of the global variable used for storing frame size. 

7. After this, reset the boolean variable to false and global variable for storing frame size to 0 so that the next frame sizes can also be computed.

Please try this and share the UART debug logs for us to check.

Best Regards,
Jayakrishna
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Tomek
New Contributor

Problem solved, i had problem on FPGA side. Thanks for your help.

Tom

View solution in original post

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JayakrishnaT_76
Moderator
Moderator

Hello,

We are glad to hear that the issue is resolved.

Best Regards,
Jayakrishna
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