cancel
Showing results for 
Search instead for 
Did you mean: 

USB Superspeed Peripherals

Anonymous
Not applicable
        Hello, we are developing our new product based on FX3 SuperSpeed controller. We will use Sync ADMUX boot option to download firmware from our master microcontroller to FX3. Referring to "AN76405 FX3 Boot Options" document I have some problems understanding the sequence for firmware download. I referred to firmware download example in this document. There are some functions (IORD_REG16(), IOWR_REG16(), IORD_SCK16() and IOWR_SCK16()) that I need some explanation what that functions do. I assume that IORD_REG16() and IOWR_REG16() reads or writes data at specified address like shown in "AN73304-ADMuxBoot" document at "Sync ADMUX Read Cycle Timing". Is that correct? If no, how do I have to set this functions to do the right job? And what does IORD_SCK16() and IOWR_SCK16() functions have to do? Thank you for your answers, Rok   
0 Likes
Reply
11 Replies
Anonymous
Not applicable

At the bottom of page 24 of the app note there is explanation for what each of these functions are meant to do

0 Likes
Reply
Anonymous
Not applicable

 Hi,

   

I already studied the description at the bottom of page 24 but it confuses me so that is why I am asking for help.

   

So please confirm me if I am right: IORD_REG16() and IOWR_REG16() functions read from and write to specified register a 16 bit word in a sequence that is shown at page 6 in document "AN73304-ADMuxBoot".

   

But what does IORD_SCK16() and IOWR_SCK16() functions do? Does they write and read in same sequence  like IORD_REG16() and IOWR_REG16()? But from what address?

   

 

   

Thank you for answers,

   

Rok

0 Likes
Reply
Anonymous
Not applicable
        The IOxx_REG16 functions do operations on registers. And the IOxx_SCK16 functions do operations on sockets. For example, in the sck_bootloader_write function given in the app note, you can see that after a bunch of register reads and writes, the data passed to the function (in the pointer "p") is written to FX3 using IOWR_SCK16(). For IOxx_REG16, the address bus (A[6:0]) will be the register's offset as given in Section 10.2 of the Programmer's Manual. And A[7] will be '1'. For IOxx_SCK16, A[6:0] will be the socket's address and A[7] == 0. See the app note or Chapter 10 of the Programmer's Manual for more details. Also look at datasheet.html in [SDK_INSTALL_PATH]\library\sync_admux.cydsn\documentation.   
0 Likes
Reply
Anonymous
Not applicable

 Thank you very much for explanation.

   

Best regards, Rok

0 Likes
Reply
Anonymous
Not applicable

 Hi,

   

I'm trying to boot FX3 via Sync ADMUX interface but with no success.

   

First, I have a question about PMODE pins. PMODE pins should be F00, so if I set jumpers J96(2-3), J97(2-3) and J98(open), is this correct for Sync ADMUX boot? All four SW25 switches are all ON.

   

My second question is about start sequence. I reffered to AN73305-ADMuxBoot where it says that at startup I you should keep polling PP_IDENTIFY register. Which register is this? I cannot find this register in FX3 Programmers Manual. Also there is no PP_IDENTIFY register in example firmware download code so what should I do about it?

   

Can somebody please help me about this problems?

   

Thanks for replies.

   

 

   

Regards,

   

Rok

0 Likes
Reply
Anonymous
Not applicable

2 RokV

   

Do you succeed with booting FX3 via GPIF 2 ?

   

I also planing this way of BOOT, but it looks like not completely verified..

0 Likes
Reply
Anonymous
Not applicable

I'm also trying to use ADMUX boot on some new prototypes and am having some problems.

   

My observations are that the register addresses given an Programmers manual table 10-1 are all in error by a factor of 4, with respect to the ADMUX bus signals.

   

eg. Bus Transactrion with Address = 0x82 (Register = 0x02) accesses PP_CONFIG (0x08)

   

Also the control signal mapping/polarity appear to be different to what I was sent.

   

I have a web case open on this.

   

I'll be interested If you are able to read the PP_CONFIG register successfully (I'm never seeing the CFGMODE bit set)

0 Likes
Reply
Anonymous
Not applicable

For those who are interested we have now got our board booting via the ADMUX interface.

   

There are a few errors/omisisons in the AN76405 documentation - I hope this will now be updated.

0 Likes
Reply
Anonymous
Not applicable

Hi,ColinSpry

   

     I'm trying to boot FX3 via Sync ADMUX interface but with no success.

   

     Can you tell me what 's the errors/omisisons in the AN76405 documentation? Can you tell me how you achieve it ?

   

    

   

 

   

     Thank you for answers,

   

      Best regards,

   

      Puck

0 Likes
Reply
Anonymous
Not applicable

The AN76405 doc has been updated since the last post on this thread. Have you taken a look at it: http://www.cypress.com/?rID=63358

   

 

   

Can you give some detail on where you are stuck?

   

Are you checking the PP_IDENTIFY / RD_MAILBOX registers after a 1ms delay after reset?

   

Or do you see an issue with a command/data read/write?

0 Likes
Reply
Anonymous
Not applicable

Hi, PRAG 

   

I have read PP_IDENTIFY / RD_MAILBOX registers, 0x81 and  0x42575943  is been reading back. NOW,  read / write register  success. but read / write socket have problem .When writing  the  command('C' 'Y' 0X02 0X01) one time or two times , the PP_SOCK_STAT_L  register always is   1.I should wirting the command('C' 'Y' 0X02 0X01)  three times , the PP_SOCK_STAT_L   register is 5 .When reading the response through the socket 2 one time , the result is 0x0. 
When reading the response through the socket 2  twice ,  the result is 'W' 'B', 0x01 0x02 .  As far as i know , the right response is ‘W' 'B' 0x* 0x0.

   

 

   

      Thank you for answers,

   

       Best regards,

   

        pcuk

0 Likes
Reply