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USB Superspeed Peripherals

GiMU_801241
New Contributor

Hello,

I can't speak English well.

In the FX3 SlaveFIFOSync 5Bit example, we want to use 6 ENDPOINTs.

 

ADDR_LINES.PNG

 

endpoints 0x1, 0x2, 0x3 works well.

 

But endpoints 0x81, 0x82, 0x83
BULK IN transfer
BULK IN transfer failed with Error Code:997 occurs.

 

I checked the 5bit FIFO ADDR
From 0 to 31, the flag of the INPUT endpoint did not occur.

Only output endpoint 0x1~0x3 operates.

 

FIFO_ADDR.PNG

 

ADDR_LINES_change.PNG

 

If you change the positions of CY_U3P_PIB_SOCKET_0 and CY_U3P_PIB_SOCKET_4, this time they all change to INPUT and OUTPUT does not work.

 

Can you explain what the problem is?

I want to use all 6 ENDPOINTs

 

Thank you.

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1 Solution
Hemanth
Moderator
Moderator

Hi,

The reason for suggesting CY_FX_NUMBER_OF_ADDR_LINES to be 5 is because we have tested that in AN68829

When 5-bit address is used, it is not mandatory that you need to have 30 channels. You can go with less than 30 also. That is why I suggested glNumberOfChannels to be 6.

Regarding the mapping:

You know that in 5-bit addressing mode, below are the PPort base address

#define CY_FX_PRODUCER_PPORT_SOCKET_BASE CY_U3P_PIB_SOCKET_16
#define CY_FX_CONSUMER_PPORT_SOCKET_BASE CY_U3P_PIB_SOCKET_0

So, if you create a P to U channel, the producer sockets can be from CY_U3P_PIB_SOCKET_16 to CY_U3P_PIB_SOCKET_31

and the consumer sockets can be from CY_U3P_PIB_SOCKET_0 to CY_U3P_PIB_SOCKET_15

for(i=0;i<(glNumberOfChannels/2);i++)
    {
        /* Create a DMA AUTO channel for P2U transfer. */
        dmaCfg.prodSckId = (CyU3PDmaSocketId_t)CyFxProducerSocket[i+15];
        dmaCfg.consSckId = (CyU3PDmaSocketId_t)CyFxConsumerSocket[i+15];

So, if you see above snippet of your code, producer for first P2U channel is CY_FX_PRODUCER_1_PPORT_SOCKET which is FX_PRODUCER_PPORT_SOCKET_BASE + CY_FX_EP_PRODUCER_1 which is CY_U3P_PIB_SOCKET_16 + 0x01 which is CY_U3P_PIB_SOCKET_17

consumer for the first channel is

CY_FX_CONSUMER_1_USB_SOCKET which is CY_FX_CONSUMER_USB_SOCKET_BASE + (CY_FX_EP_CONSUMER_1 & 0xF) which is CY_U3P_UIB_SOCKET_CONS_0 + 0x01 - which would be for EP1IN

In this way, if glNumberOfChannels is 6, above snippet will create following channels:

CY_U3P_PIB_SOCKET_17 will be mapped to EP1-IN

CY_U3P_PIB_SOCKET_18 will be mapped to EP2-IN

CY_U3P_PIB_SOCKET_19 will be mapped to EP3-IN

And as per section 4 of AN68829, "Note that the P-port socket number in the DMA channel should be the logical socket number that will be addressed on A4:A0."

So to access PIB socket 17 you will have to drive A4:A0 as 10001 (You can see Figure 4 of app note)

Regards,

Hemanth

View solution in original post

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12 Replies
Hemanth
Moderator
Moderator

Hi,

Let CY_FX_NUMBER_OF_ADDR_LINES be 5

Assign value 6 to glNumberOfChannels

Then your channels will be the following:

CY_U3P_PIB_SOCKET_17 will be mapped to EP1-IN

CY_U3P_PIB_SOCKET_18 will be mapped to EP2-IN

CY_U3P_PIB_SOCKET_19 will be mapped to EP3-IN

Regards,

Hemanth
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GiMU_801241
New Contributor

답변 해주셔서 감사합니다

그러나 나는 당신이 말하는 것을 이해하기가 어렵습니다.

CY_FX_NUMBER_OF_ADDR_LINES = 5로 설정하고 glNumberOfChannels를 6으로 설정합니까?

glNumberOfChannels.PNG

CY_FX_NUMBER_OF_ADDR_LINES = 3을 사용할 수 없습니까?

 

 

 

 

CY_U3P_PIB_SOCKET_17, CY_U3P_PIB_SOCKET_18, CY_U3P_PIB_SOCKET_19의 매핑을 이해하기 어렵습니다.

socket_base.PNGsocket_base2.PNG

 

 

 

 

 

 

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Hemanth
Moderator
Moderator

Hi,

The reason for suggesting CY_FX_NUMBER_OF_ADDR_LINES to be 5 is because we have tested that in AN68829

When 5-bit address is used, it is not mandatory that you need to have 30 channels. You can go with less than 30 also. That is why I suggested glNumberOfChannels to be 6.

Regarding the mapping:

You know that in 5-bit addressing mode, below are the PPort base address

#define CY_FX_PRODUCER_PPORT_SOCKET_BASE CY_U3P_PIB_SOCKET_16
#define CY_FX_CONSUMER_PPORT_SOCKET_BASE CY_U3P_PIB_SOCKET_0

So, if you create a P to U channel, the producer sockets can be from CY_U3P_PIB_SOCKET_16 to CY_U3P_PIB_SOCKET_31

and the consumer sockets can be from CY_U3P_PIB_SOCKET_0 to CY_U3P_PIB_SOCKET_15

for(i=0;i<(glNumberOfChannels/2);i++)
    {
        /* Create a DMA AUTO channel for P2U transfer. */
        dmaCfg.prodSckId = (CyU3PDmaSocketId_t)CyFxProducerSocket[i+15];
        dmaCfg.consSckId = (CyU3PDmaSocketId_t)CyFxConsumerSocket[i+15];

So, if you see above snippet of your code, producer for first P2U channel is CY_FX_PRODUCER_1_PPORT_SOCKET which is FX_PRODUCER_PPORT_SOCKET_BASE + CY_FX_EP_PRODUCER_1 which is CY_U3P_PIB_SOCKET_16 + 0x01 which is CY_U3P_PIB_SOCKET_17

consumer for the first channel is

CY_FX_CONSUMER_1_USB_SOCKET which is CY_FX_CONSUMER_USB_SOCKET_BASE + (CY_FX_EP_CONSUMER_1 & 0xF) which is CY_U3P_UIB_SOCKET_CONS_0 + 0x01 - which would be for EP1IN

In this way, if glNumberOfChannels is 6, above snippet will create following channels:

CY_U3P_PIB_SOCKET_17 will be mapped to EP1-IN

CY_U3P_PIB_SOCKET_18 will be mapped to EP2-IN

CY_U3P_PIB_SOCKET_19 will be mapped to EP3-IN

And as per section 4 of AN68829, "Note that the P-port socket number in the DMA channel should be the logical socket number that will be addressed on A4:A0."

So to access PIB socket 17 you will have to drive A4:A0 as 10001 (You can see Figure 4 of app note)

Regards,

Hemanth

View solution in original post

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GiMU_801241
New Contributor

hi

Thank you for your kind answer.

I used to check the FIFO ADDR. However, there seems to be another problem with FLAG A&B.

 

FIFO_ADDR_a.PNG

I think you should check the generated file of GPIF II Designer.

I'll check a little more and ask again

Thank you.

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Hemanth
Moderator
Moderator

Hi,

Can you please let me know what is the issue now? Is the original problem resolved?

Regards,

Hemanth
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GiMU_801241
New Contributor

Hello.

The problem has not been resolved yet.

When data is transmitted to endpoint 0x1, 0x2, 0x3 in all FIFO ADDR
FLAG A is in the'High' state. If there is no transmission, it is in the'low' state.

However, in the input state (write mode), the address FLAG A of FIFO ADDR "10001", "10010" and "10011" is in the'Low' state, not the'high' (Not Full) state.

 

 

slavefifo_write.PNG

 

Best Regards,

Gijun MUN

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Hemanth
Moderator
Moderator

Hi Gijun Mun,

Can you please share your channel configuration?

When data is transmitted to endpoint 0x1, 0x2, 0x3 in all FIFO ADDR
FLAG A is in the'High' state. If there is no transmission, it is in the'low' state.

>> From this I think OUT endpoints are working fine.

However, in the input state (write mode), the address FLAG A of FIFO ADDR "10001", "10010" and "10011" is in the'Low' state, not the'high' (Not Full) state.

>> Please share your channel and endpoint configuration done in your firmware.

Regards,

Hemanth
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GiMU_801241
New Contributor

Hi Hemanth,

Currently, I tested 0x1 & 0x81 with 2bit slavefifo.
Works well.

But I couldn't configure 6 endpoints...

Now we will start testing again to configure 6 endpoints.

 

I will share the source code.

 

 

Best Regards,

Gijun MUN

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Hemanth
Moderator
Moderator

Hi Gijun Mun,

If 6 PIB sockets are being used, then please try with 5 address lines.

Let me know after you test.

Also please share your gpif project if you are facing the flag issue after testing.

Regards

Hemanth
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GiMU_801241
New Contributor

Hi Hemanth,

The address line is set to 5.

I haven't solved the FLAG problem yet.

Share GPIF files.

 

Best Regards,

Gijun MUN

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Hemanth
Moderator
Moderator

Hi,

The producer sockets used for the PtoU channels are 17, 18 and 19 (when glNumberOfChannels is 6)

So, valid addresses for these PtoU channels are 10001, 10010 and 10011

Did you use EPSWITCH to map physical socket 4 to Thread 1, 2 and 3? (Because by default physical socket 0 is mapped to the threads. See section 4.3 of AN68829)

Regards,

Hemanth
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GiMU_801241
New Contributor

Hi

I didn't use EPSWITCH.

Currently I haven't used slavefifo 5bit. Transmission test was performed using 4 ENDPOINTs in slavefifo 2bit.

Due to the development time, I cannot use slavefifo 5bit and are satisfied with using 4 ENDPOINTs in slavefifo 2bit.

Next time I have a chance, I will try debugging again.

In the meantime, thank you for the answer.

Regards,

Gijun MUN

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