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I have question about the FX3 clock setting when using slave fifo to transfer data from FPGA to PC. Should the the clock frequency match with the data sending speed? Data was from a A/D converter which is at 20 MHz, while FX3 clock was set at 100 MHz. When I enabled the A/D module (AD_OE = 0), it was unable to transfer the data and throw the 997 error code. When AD_OE = 1, pins were in high-impedance state, FX3 was able to transfer data with all FF FF. I modified the stream-IN example.
Code 997 represents a timeout error. That means that the host did not receive the data, and the Xfer fails. FX3 can run at its 100MHz. You need to make sure that the FX3 has data. IF FX3 does not have data, then you will get error 997 on the host. So, please make sure that the ADC is sending data and the DMA is receiving it. Please check in the DMA callback if you get a PROD event (which shows that a buffer became full). What is the size of the data from the ADC, and what is the DMA size. If the data is less that the DMA buffer size, then the buffer will not get committed automatically. Please make sure that in such cases, you do commit it manually (though commit action in the GPIF). FFFF is the default values, if you sample the GPIF pins without any actual data, then you will see FF FF. What is you GPIF state machine, please share it.