I config FX3 as Slave FIFO 32bit.
If I set FLAGA is Thread_0_DMA_Ready, FLAGB is Thread_0_DMA_Watermark, and set watermark as 4.
Assume DMA buffer is 1024*4.
Because the write is random, I assume the flowing steps:
1. Write 1019 words to fifo;
2. Because no data, wait some cycles;
3. Write 2 words to fifo; (I think FLAGB is not active, because 3 cycles latency)
4. Because no data, wait some cycles, now FLAGB is active;
5. Now data arrived, but we cannot know how many space at DMA buffer? FLAGB=L, FLAGA=H, ( actual has 3 words space);
I think, at step 5, we can only use single write cycle? For example, write one word, and wait 4 cycles, then check the FLAGA?
The formula in An65974 application note says:
When writing from an external master to the synchronous Slave FIFO: (a) The number of data words that may be written after the clock edge at which the partial flag is sampled low = watermark x (32/bus width) – 4
So, no. of words after FLag B low = 4 * 32/32 - 4 = 0
This means in your case, after Flag B has reached low, you can no longer write any more data. This means in your case, the Flag B becomes low only after 1024th byte is written. (In your case size of each buffer is 1024 as you mentioned)
So after 1019, you can still write 5 more bytes (ofcourse you can wait in between if you do not have Data)/.. Only after that the flag B samples low.
- Madhu Sudhan
Thanks for your reply.
But I think you don't catch my question.
I put the waveform here.
The configuration of waveform is: DMA buffer size if 16384,and watermark is 4.
FLAGA is Thread_0_DMA_Ready, FLAGB is Thread_0_DMA_Watermark
So I think for random write access, if watermark is actived, we can only use single write and delay 4 cycles to check FLAGA.