Dear Support Team,
As per FX3 Data Sheet (http://www.cypress.com/file/140296/download) Pin Description (Page 17, Table 7. CYUSB3012 and CYUSB3014 Pin List), RESET# signal is connected to “CVDDQ” IO Bank.
But, As per FX3 Schematics (http://www.cypress.com/file/114711/download), RESET# signal is connected to “VIO1” IO Bank, though it is pulled high with "CVDDQ" supply.
Is there a mistake in the FX3 Schematics ??
I don't find in the schematics that Reset signal is associated to the VIO1 power domain. Can you please specify where exactly on the schematics do you see this?