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I am working on a project which need transfer data from pc to FPGA. I used the slave FIFO.
the configure is:
16bits GPIF bus
DMA buffer size = 16K
DMA buffer COUNT = 4
DMA mode : AUTO
if the PFGA runs at higher speed than the usb host OUT speed, the system runs very well. when the FPGA runs at a lower speed than the USB OUT speed, the transfer process can only run for several package and then blocked.
It seems that if the FPGA runs at lower speed than USB OUT speed, the all 4 DMA buffers have a risk to be all filled, once all the 4 DMA buffers are all filled, the AUTO OUT process terminate and can NOT recover.
is this correct? if this is the case, how to make the process keep on going instead of termination when all 4 DMA buffers are filled ?
From the debug prints, I observed that there a difference between the data received and data consumed which can be a reason issue (streamer App failures) as there is DMA buffer overflow.
Data tracker: RX count: 3834, TX count: 3834.
Data tracker: RX count: 4110, TX count: 3926. // possible reason
Data tracker: RX count: 4110, TX count: 4110.
- Please try increasing the DMA buffer size to 32 K and DMA buffer count as 6. This should solve the problem.
- To confirm the problem you can also try changing the DMA channel to manual channel and check that is there commit buffer failure with error code CY_U3P_ERROR_INVALID_SEQUENCE
Status = CyU3PDmaChannelCreate(&USB2GPIF_Handle, CY_U3P_DMA_TYPE_MANUAL , &dmaConfig);
And commit the DMA buffers manually. If the DMA buffers are already full (not consumed by FPGA) and still data is being sent from the USB the CyU3PDmaChannelCommitBuffer API will fail. You can see the debug prints if this fails.
CyU3PReturnStatus_t status = CY_U3P_SUCCESS;
if (type == CY_U3P_DMA_CB_PROD_EVENT)
status = CyU3PDmaChannelCommitBuffer (chHandle, input->buffer_p.count, 0);