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USB Superspeed Peripherals

xuxinhang
New Contributor

When I use GPIF-II sync slave fifo interface with 2-bit address mode, I can successfully set watermark values for the four threads / P-port sockets. Just like the following:

 

    CyU3PGpifSocketConfigure (0, CY_FX_PRODUCER_1_PPORT_SOCKET, 6, CyFalse, 1);
    CyU3PGpifSocketConfigure (1, CY_FX_PRODUCER_2_PPORT_SOCKET, 6, CyFalse, 1);
    CyU3PGpifSocketConfigure (2, CY_FX_PRODUCER_3_PPORT_SOCKET, 6, CyFalse, 1);
    CyU3PGpifSocketConfigure (3, CY_FX_CONSUMER_1_PPORT_SOCKET, 5, CyFalse, 1);

 


And now, I switch to 5-bit address mode for more transfer endpoints. And I want to set watermark values for each P-port sockets. Here are fourteen P-ports. However the following code is not availbale.

 

    CyU3PGpifSocketConfigure (0, CY_FX_PRODUCER_1_PPORT_SOCKET, 6, CyFalse, 1);
    CyU3PGpifSocketConfigure (1, CY_FX_PRODUCER_2_PPORT_SOCKET, 6, CyFalse, 1);
    CyU3PGpifSocketConfigure (2, CY_FX_PRODUCER_3_PPORT_SOCKET, 6, CyFalse, 1);
    CyU3PGpifSocketConfigure (3, CY_FX_CONSUMER_1_PPORT_SOCKET, 5, CyFalse, 1);
    CyU3PGpifSocketConfigure (0, CY_FX_CONSUMER_2_PPORT_SOCKET, 5, CyFalse, 1);
    CyU3PGpifSocketConfigure (1, CY_FX_CONSUMER_3_PPORT_SOCKET, 5, CyFalse, 1);
    CyU3PGpifSocketConfigure (2, CY_FX_PRODUCER_4_PPORT_SOCKET, 6, CyFalse, 1);
    CyU3PGpifSocketConfigure (3, CY_FX_PRODUCER_5_PPORT_SOCKET, 6, CyFalse, 1);
    CyU3PGpifSocketConfigure (0, CY_FX_PRODUCER_6_PPORT_SOCKET, 6, CyFalse, 1);
    CyU3PGpifSocketConfigure (1, CY_FX_PRODUCER_7_PPORT_SOCKET, 6, CyFalse, 1);
    CyU3PGpifSocketConfigure (2, CY_FX_CONSUMER_4_PPORT_SOCKET, 5, CyFalse, 1);
    CyU3PGpifSocketConfigure (3, CY_FX_CONSUMER_5_PPORT_SOCKET, 5, CyFalse, 1);
    CyU3PGpifSocketConfigure (0, CY_FX_CONSUMER_6_PPORT_SOCKET, 5, CyFalse, 1);
    CyU3PGpifSocketConfigure (1, CY_FX_CONSUMER_7_PPORT_SOCKET, 5, CyFalse, 1);

 

Then no data can be transfered through any P-ports.

 

So, I wonder what's the correct way to assign watermark values for P-ports - under 5-bit address mode.

 

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3 Replies
AliAsgar
Moderator
Moderator

Hello,

1. Could you share your firmware project folder with us?(including the GPIF project)

2. Could you give more information on how the data transfer happens. What is the application?

3. How are the address lines been driven?

Best Regards,
AliAsgar

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xuxinhang
New Contributor

Here is my source code. See the attchment.

... and in this post, I'd like to share more details about my way to operate GPIF, which

There are 14 P-ports are connected to 14 U-ports, but only two WR P-port used in my experiment - "addr=2" and "addr=6". So I have to use EPSWITCH# signal to switch thread 2 between the two logical sockets, in FPGA.

First, I use only the socket 2 and thread 2. First FPGA sets ADDR, waits for a while, check flag signals (FLAGA = current thread ready and FLAGB = current thread watermark), and decides whether to start to transfer. During writting to the socket, once FLAGB asserted, PKTEND# will assert to end this packet. Just like the following figure. That works fine and the computer can receive all of data correctly.

捕获4.PNG

Then, I use the two socket in turns. Socket 2 is still applied with the same transfer pattern. Socket 6 is always fed with single word packets. However, only data fed into socket 6 can be steadily read out via corresponding USB endpoint and data of socket 2 cannot be read through USB endpoint except the first ~4M data.

That's awkward. I probed inner signals in FPGA and I found the two GPIF flag signals seems wired. Please see the following screenshot. FLAGA is expected to be high because the USB endpoint has used up, which could indicate the DMA buffer to be empty.

Besides, this screenshot also shows the timing for accessing GPIF and its sockets.

捕获5.PNG

I cannot work out why. Could you please explain what causes this problem? Or does I misunderstand something?

Thanks.

 

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AliAsgar
Moderator
Moderator

Hello,

1. Could you probe the interface lines and check whether FPGA is driving the lines properly?

2. Could you also add the timing diagram of the addr field in the second timing diagram you have shared in the previous post.

3 By 4M, you mean 4M bits or 4M bytes?

4. Could you share with us the number of prod and cons events occurring during the transfer?

Best Regards,
AliAsgar

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