Showing results for 
Search instead for 
Did you mean: 

USB Superspeed Peripherals



I'm referencing SlaveFifoSync firmware.

In cyfxslfifosync.c, line 887, it's enable GPIO 59 as below.

    /* No GPIOs are enabled. */

    io_cfg.gpioSimpleEn[0]  = 0;

    io_cfg.gpioSimpleEn[1]  = 0x08000000; /* GPIO 59 */

    io_cfg.gpioComplexEn[0] = 0;

    io_cfg.gpioComplexEn[1] = 0;

My questions are

1. Why GPIO 59 is enabled? Since I can't find it from GPIF Designer.


2. What's the general guiding rules for GPIO initialisation.


1 Solution


- The GPIO 59 is used as a RESET pin for the FPGA. Please refer to section 10.2 in the AN65974 Application Note document.

- General steps to configure a GPIO pin:

    1. Enable the GPIO pins by initializing the CyU3PIoMatrixConfig_t structure (gpioSimpleEn and gpioComplexEn) and passing it as parameter to the CyU3PDeviceConfigureIOMatrix() API. Depending on the configuration of the GPIF II, certain GPIO pins belong to the GPIF II interface and are not directly available as simple GPIOs. In order to use these GPIOs, the CyU3PDeviceGpioOverride() API needs to be used.

    2. The GPIO clock needs to enabled using the CyU3PGpioInit() API along with its structure parameter.

    3. Configure the GPIO using the CyU3PGpioSetSimpleConfig() API along with its associated parameters.

    4. The value to be driven on the GPIO can be set using the CyU3PGpioSetValue() API. In case a simple GPIO pin is used, the CyU3PGpioSimpleSetValue() API can also be used since this will be faster.

Kindly, refer to the FX3 API Guide document for details on the parameters of the API. For reference implementation of the above mentioned procedure, refer to GpioApp example firmware that comes with the FX3 SDK.

Best regards,

Srinath S

View solution in original post

1 Reply