FX3 GPIF Slave PCLK Problem

[wudic_1035111]

Hello,

I'm using FX3 to communicate with FPGA with a PCLK signal generated by FPGA side. In the past, our product is working fine with PCLK = 74.25MHz, and now we are trying to speed up the PCLK to 100M. Without modification on the FX3 firmware, and directly increase PCLK frequency, we found following problem:

1. Total byte count is correct, but part of the packet data is shifted about 52 bytes latter(not fixed), event the packet is smaller than the DMA buffer size and WM is not related. But the last 32bytes of data are always correct.

2. Sending a packet larger than DMA buffer size, ready and WM stuck forever even PC side read data continuously.

We've checked the slack and time sequence on the FPGA side but found nothing. The output of FPGA data is not shifted. Is there anything I need to update for the change of PCLK?

Thanks,

W.D.

[wudic_1035111]

I've changed setSysClk400 to be true, which was false, but data is still incorrect, while in a different way.

[wudic_1035111 · Accepted solution]

Hi, problem has been solved. after change setSysClk400 to be true, system works well. The former problem was a test bench bug.