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USB Superspeed Peripherals

ReBa_1054056
New Contributor

I have a FX3S design which functions like a camera and can operate in a recording mode (when USB is disconnected) and in mass storage mode (when USB is connected).

During the mass storage mode the recorded data can be read from the SD.

During the recording mode the CPU uses a AUTO DMA channel to pass the data from the PIB (GPIF) to the SD. Besides this the CPU can also use a MANUAL_IN and MANUAL_OUT DMA channel to pass 512 command bytes from PIB to the CPU memory and from the CPU memory to PIB. This all functions without any problem when USB is disconnected.

When the recording mode is used (for debugging) when the USB is connected, the data is not passed on to the SD but to an USB bulk IN endpoint. The 512 command bytes can also be transferred back and forth between CPU and PIB using the same DMA channels as in the USB disconnected state. This MANUAL_IN DMA transfer using CyU3PDmaChannelSetupRecvBuffer however only works when connected to a USB3.0 superspeed PC port, and not when connected to a USB2.0 highspeed PC port.

In the case of the highspeed connection the DMA status (using CyU3PDmaChannelGetStatus) remains in 0x4 (= CY_U3P_DMA_CONS_OVERRIDE). In case of a superspeed connection everything works fine and the 512 bytes are transferred.

What is changed within the FX3 or FX3S regarding to the DMA from PIB to CPU when using highspeed compared to superspeed?

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1 Solution
YatheeshD_36
Moderator
Moderator

Hello,

Please refer to this KBA which explains all about the DMA channel in override mode: DMA Channel in Override Mode in FX3/CX3 - KBA229098

The CY_U3P_DMA_CONS_OVERRIDE mode indicates that the transfer is not yet complete.

You can use the CyU3PDmaChannelWaitForRecvBuffer API to wait for the completion of the transfer and then proceed after a success return from the API.

Thanks,

Yatheesh

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5 Replies
YatheeshD_36
Moderator
Moderator

Hello,

Please refer to this KBA which explains all about the DMA channel in override mode: DMA Channel in Override Mode in FX3/CX3 - KBA229098

The CY_U3P_DMA_CONS_OVERRIDE mode indicates that the transfer is not yet complete.

You can use the CyU3PDmaChannelWaitForRecvBuffer API to wait for the completion of the transfer and then proceed after a success return from the API.

Thanks,

Yatheesh

View solution in original post

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ReBa_1054056
New Contributor

Hello Yatheesh,

After the CyU3PDmaChannelSetupRecvBuffer I use CyU3PEventGet to receive the event which is Set by the DMA cb (call back) in response to the CY_U3P_DMA_CB_SEND_CPLT event from the DMA channel. This event is however never send, as the DMA channel is not yet complete. And CyU3PDmaChannelGetStatus reports a prodXferCount of 0. The transfer simply never ends.

Btw I also use CyU3PDmaChannelWaitForRecvBuffer to be sure the DMA channel has completed.

When I use CYU3P_WAIT_FOREVER with this CyU3PEventGet it waits forever and the application hangs.

This only happens after an USB highspeed enumeration.

The strangest thing is that when I perform one dummy DMA transfer of this DMA channel the enumeration to highspeed has no negative effect on this situation, and all additional transfers are performed without any hang situation. Without this dummy DMA transfer the enumeration to highspeed seems to do something causing the unused DMA channel to hang. But the USB enumeration should have no effect on unrelated DMA channels.

So in principal I have a workaround.

Regards,

Rene

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YatheeshD_36
Moderator
Moderator

Hello Rene,

Can you please share the .c file where the CyU3PConnectState() API is called?

Thanks,

Yatheesh

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ReBa_1054056
New Contributor

Hello Yatheesh,

I have used the FX3SMassStorage reference design (for the Pactron board). So the cyfx3s_msc.c is about the same as the .c file where the CyU3PConnectState() API is called.

What are you looking for, or what do you want to check.

The largest part of the design is propitiatory, so I will not be able to share this.

Regards,

René

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YatheeshD_36
Moderator
Moderator

Update:

The issue was resolved by adding a additional state in the State Machine to monitor the DMA thread ready states.

Thanks,

Yatheesh

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