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USB Superspeed Peripherals

WaRa_4824346
New Contributor

Our application requires following "devices" to be supported on one USB link:

1. One audio device without I2S.  Streaming data will be sent and received through the GPIF II interface

2. One SPI device

3. One I2C

4. One UART

Support of items 2,3,4 above will not allow the use of 32 bits on the GPIF II interface.  Sixteen bit transfers will be sufficient. 

Questions:

1.  How is the FX3's 16 Data + UART + SPI + I2S operation mode selected?  Software running on the FX3?  Hardware?

2. When the 16 Data + UART + SPI + i2S operation mode is selected are GPIOs mapped onto DQ[16} to DQ[27] functional?

3. Can the UART + SPI + GPIF II interfaces be used simultaneously?  Of course, transfers on the USB bus can only be for one interface at a time but can the USB Host software "open" all of these interfaces and transfer data as required? Or, will the USB host be forced to "close" one USB device before it "opens" another?

4. When implementing USB bridging functions, how many endpoints are required per bridge?  I believe 1 Control Endpoint + 3 (In, Out, Interrupt)  is required per bridge.  Implementing four USB to UART bridges would require 13 endpoints. One control endpoint shared by all UART bridges plus 12 more endpoints (4 x In, Out and Interrupt endpoints).  Is my understand correct?

Thanks for your help,

Wayne

 

 

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1 Solution
Rashi_Vatsa
Moderator
Moderator

Hello Wayne,

Please find my comments below

1.  How is the FX3's 16 Data + UART + SPI + I2S operation mode selected?  Software running on the FX3?  Hardware?

>>  The configuration is done in   io matrix configuration of the  firmware

In the example code, only UART is enabled (io_cfg.useUart = CyTrue;)and GPIF bus width is set to 16 bits ( io_cfg.isDQ32Bit = CyFalse;)

CyU3PMemSet ((uint8_t *)&io_cfg, 0, sizeof(io_cfg));
    io_cfg.isDQ32Bit = CyFalse;
    io_cfg.s0Mode    = CY_U3P_SPORT_INACTIVE;
    io_cfg.s1Mode    = CY_U3P_SPORT_INACTIVE;
    io_cfg.useUart   = CyTrue;
    io_cfg.useI2C    = CyFalse;
    io_cfg.useI2S    = CyFalse;
    io_cfg.useSpi    = CyFalse;
    io_cfg.lppMode   = CY_U3P_IO_MATRIX_LPP_DEFAULT;

    /* No GPIOs are enabled. */
    io_cfg.gpioSimpleEn[0]  = 0;
    io_cfg.gpioSimpleEn[1]  = 0x00000040;
    io_cfg.gpioComplexEn[0] = 0;
    io_cfg.gpioComplexEn[1] = 0;
    status = CyU3PDeviceConfigureIOMatrix (&io_cfg);
    if (status != CY_U3P_SUCCESS)
    {
        goto handle_fatal_error;
    }

 

2. When the 16 Data + UART + SPI + i2S operation mode is selected are GPIOs mapped onto DQ[16} to DQ[27] functional?

>> In this cofiguration, GPIO [33] to GPIO[45] can be used as GPIOs

3. Can the UART + SPI + GPIF II interfaces be used simultaneously?  Of course, transfers on the USB bus can only be for one interface at a time but can the USB Host software "open" all of these interfaces and transfer data as required? Or, will the USB host be forced to "close" one USB device before it "opens" another?

>> UART + SPI can be used when GPIF bus width is 16 bits. All of them can be used simultaneously.

4. When implementing USB bridging functions, how many endpoints are required per bridge?  I believe 1 Control Endpoint + 3 (In, Out, Interrupt)  is required per bridge.  Implementing four USB to UART bridges would require 13 endpoints. One control endpoint shared by all UART bridges plus 12 more endpoints (4 x In, Out and Interrupt endpoints).  Is my understand correct?

>> By bridge do you mean the DMA channel between SPI > USB, UART > USB?

A USB device can have only 1 Control endpoint i.e. endpoint 0. The number of endpoints would depend on the application. Please let me know more about the "bridge" and application.

 

Regards,
Rashi

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1 Reply
Rashi_Vatsa
Moderator
Moderator

Hello Wayne,

Please find my comments below

1.  How is the FX3's 16 Data + UART + SPI + I2S operation mode selected?  Software running on the FX3?  Hardware?

>>  The configuration is done in   io matrix configuration of the  firmware

In the example code, only UART is enabled (io_cfg.useUart = CyTrue;)and GPIF bus width is set to 16 bits ( io_cfg.isDQ32Bit = CyFalse;)

CyU3PMemSet ((uint8_t *)&io_cfg, 0, sizeof(io_cfg));
    io_cfg.isDQ32Bit = CyFalse;
    io_cfg.s0Mode    = CY_U3P_SPORT_INACTIVE;
    io_cfg.s1Mode    = CY_U3P_SPORT_INACTIVE;
    io_cfg.useUart   = CyTrue;
    io_cfg.useI2C    = CyFalse;
    io_cfg.useI2S    = CyFalse;
    io_cfg.useSpi    = CyFalse;
    io_cfg.lppMode   = CY_U3P_IO_MATRIX_LPP_DEFAULT;

    /* No GPIOs are enabled. */
    io_cfg.gpioSimpleEn[0]  = 0;
    io_cfg.gpioSimpleEn[1]  = 0x00000040;
    io_cfg.gpioComplexEn[0] = 0;
    io_cfg.gpioComplexEn[1] = 0;
    status = CyU3PDeviceConfigureIOMatrix (&io_cfg);
    if (status != CY_U3P_SUCCESS)
    {
        goto handle_fatal_error;
    }

 

2. When the 16 Data + UART + SPI + i2S operation mode is selected are GPIOs mapped onto DQ[16} to DQ[27] functional?

>> In this cofiguration, GPIO [33] to GPIO[45] can be used as GPIOs

3. Can the UART + SPI + GPIF II interfaces be used simultaneously?  Of course, transfers on the USB bus can only be for one interface at a time but can the USB Host software "open" all of these interfaces and transfer data as required? Or, will the USB host be forced to "close" one USB device before it "opens" another?

>> UART + SPI can be used when GPIF bus width is 16 bits. All of them can be used simultaneously.

4. When implementing USB bridging functions, how many endpoints are required per bridge?  I believe 1 Control Endpoint + 3 (In, Out, Interrupt)  is required per bridge.  Implementing four USB to UART bridges would require 13 endpoints. One control endpoint shared by all UART bridges plus 12 more endpoints (4 x In, Out and Interrupt endpoints).  Is my understand correct?

>> By bridge do you mean the DMA channel between SPI > USB, UART > USB?

A USB device can have only 1 Control endpoint i.e. endpoint 0. The number of endpoints would depend on the application. Please let me know more about the "bridge" and application.

 

Regards,
Rashi

View solution in original post

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