FX3 Address latch enable

[TeMa_2997106]

Is it necessary to add ALE with GPIF2 when FX3 is Slave?
Is it possible to always enable the operation?

Thanks,
Tetsuo

[Rashi_Vatsa]

Hello Tetsuo san,

Is it necessary to add ALE with GPIF2 when FX3 is Slave?

>> Adding ALE  will depend on your application. The Slave FIFO (AN65974) state machine doesn't use ALE when FX3 is configured as a slave.

ALE: Address Latch Enable is input to FX3. Enables the input address stage on the FX3 to latch address values. It is only available for asynchronous interface. ALE is used by the external processor (master) to notify the slave that the address bus is enabled generally when address bus and data bus are multiplexed.

Is it possible to always enable the operation?

>> Please let me know more about the application. 

[TeMa_2997106]

Rashi-san,

I am considering replacing the Renesas USB controller (M66291GP) with FX3. I want to use Async SRAM. no use Slave FIFO.

I think this mode has not multiplexed addresses and data. Therefore, I think that ALE is unnecessary. Is it correct?

Thanks,
Tetsuo

[Rashi_Vatsa]

Hello Tetsuo san,

As in your application the data lines and address lines are not multiplexed, ALE can be removed. The ASYNC SRAM state machine of the SDK doesn't use ALE as the data lines and address lines are not multiplexed.

In this state machine, CE and WE signals are used to transition to the state where IN_ADDR (reading address lines) action is called instead of ALE. The signals from the SRAM to FX3 will be used to control the transitions to GPIF state in the GPIF state machine.

[TeMa_2997106]

Rashi-san,

Thank you for your reply. I understand.

Unfortunately, I haven't got more information about Async RAM yet. I asked a question here. If  I  get that information, I will check it .

Thanks,

Tetsuo

[Rashi_Vatsa · Accepted solution]

Hello Tetsuo san,

The thread you pointed to discusses about SRAM boot. But for application firmware you can use async sram for understanding that the interfacing signals can be used for reading the address and data from gpif bus. FX3 SDK has template GPIF state machines which includes Async SRAM (FX3 SDK \Cypress\EZ-USB FX3 SDK\1.3\GPIFII Designer\library\async_sram.cydsn)

You can refer to that state machine for understanding