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USB Superspeed Peripherals

JCL
New Contributor II

Hi,

We intend to use a camera module (sensor + FPGA) with the FX3 and UVC to the Host like in AN75779.
The module outputs VGA@60fps but has a pretty low pixel clock (20MHz).

I’m trying to check if the module timing is compatible with the GPIF state machine as described in AN75779.
I’m struggling to find information in the spec/appnote/community on the shortest horizontal and vertical blanking times or clock cycles required.

As far as I understand AN75779 GPIF state machine:

  • The horizontal blanking must be at least 2 pixel clocks as everything happens within the GPIF state machine going through LINE_END_SCK0/1 state chains
  • The vertical blanking must be much longer as it involves interrupt in the FX3 CPU and SW back triggering of the GPIF state machine (next to pixel clocks required to progress in the state machine).

Is my understanding correct ?
Is there a minimum time (for a given CPU clock) I can take in account for the vertical blanking?

Thanks in advance
JC

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1 Solution
JayakrishnaT_76
Moderator
Moderator

Hello JC,

Yes, your understanding is correct.

We recommend that you keep a minimum vertical blanking time of 500uS while using AN75779 state machine to acquire data without any loss.

Best Regards,
Jayakrishna

View solution in original post

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2 Replies
JayakrishnaT_76
Moderator
Moderator

Hello JC,

Yes, your understanding is correct.

We recommend that you keep a minimum vertical blanking time of 500uS while using AN75779 state machine to acquire data without any loss.

Best Regards,
Jayakrishna

View solution in original post

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JCL
New Contributor II

Hi,

Thanks for a lot your answer (in such a quick time).

Best regards,
JC

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