I am working on the Slave FIFO stream-in of the FX3 superspeed explorer kit. I am asking if the firmware can work with 8-bits since I noticed head file only had 16 /32 bits choices. The GPIF II has the 8-bits choice.
1. How shall I modify the head files?
2. If system was configured with 32 bit, but each sending data size (from FPGA to FX3) only has 8-bit (D0-D7), is this the reason cause the 997 error?
Error 997 in the control center corresponds to a timeout error. Please check if you are getting a Prod event in the DMA callback.
You can use 8 bit interface. You need to modify the GPIF project for 8 bit mode (in the firmware you need to set isDQ32Bit to False). You will also need to change the watermark values. The description to set watermark is mentioned in AN65974 table 4. Please try and let us know if you see any problem. Make sure that the FX3 PROD event. For, this make sure that the control signals from the FPGA is moving the FX3 state to in_data state ( CyU3PGpifGetSMState API). If the state mahcine is going to in_data state, please count how many time it went there (you can have a counter for debugging, GPIF allows you to have 2 counters. You need to increment the counter at each in_data. If you do in_data enough number of times to fill the dma buffer, you will get a prod event. You can try just by reduing the DMA buffer sizes as well- small DMA buffer will fill with less in_data). Please observe the flag behavior and let us know if you see any discrepancy in the behavior.
Thank you for your reply. According to the AN65974 table 4 and the general formulae for using partial flags, the watermark for 8 bits is 1.5
2 = 1.5*(32/8) - 4
It seems the 1.5 is an invalid number for CyU3PGpifSocketConfigure(), FLAGA is configured as Thread_0_DMA_Ready, FLAGB is configured as Thread_0_DMA_watermark.
For this configuration with 8bits, the control center can only receive eight 16384-buffers (I think this is because the DMA was set as 8). And the flaga and flagb were always high. Looked like the fx3 was freezed.
BTW I have tested both 16bits and 32bits, both of them worked fine. Not sure how to deal with the 8bits.
It is not a general requiement that the watermark needs to be 2. It can be anything more as well. The application processor (FPGA), need to know what is the watermark setting and accordingly read/write the data. Lets say in the Socket configure, you have set the watermark to 6, then the number of data words that may be written after the clock edge at which the partial flag is sampled low = watermark x (32/bus width) – 4 = (6 * 32/8) -4 = 24-4 = 20. So, you can set any watermark value and accordingly have the FPGA sample for 20 or 2 cycles after the watermark flag. So, for 8 bit, you need to set the watermark in the CyU3PGpifSocketConfigure, and also you need to change the FPGA code for the set watermark. Let me know for any questions.