EZ-USB FX3 reset timing during powering up.

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
AtHa_4837446
Level 1
Level 1
5 sign-ins First reply posted First question asked

Hi Cypress experts,

I'm developing a FX3 app to use super speed. For my booting condition is loading from SPI (PMODE[2..0]=0Z1). I'd like to know the exact timing of FX3 reset. I attached estimated voltage figure when it powers up.

The main question are as follows;
1) where t_rst addressed(when RESET_N will valid)?
2) when POR ignites?
3) after POR, bootloader block works immediately, and loading starts? (the block shown under fig. in attached png)
I know in the specification, all of the condition will be set within 1ms, however, real power up time is not set under 1ms. So we should select proper RC value on RESET_N pin. I'd like to understand real mechanism of powering up.

fx3_pwr-up.png

Thanks,

0 Likes
1 Solution

Hello,

The designed RC=10k, 0.1uF.  Yes, CVDDQ domain is connected to 3.3V system.

>> Please let me know if the reset time can be increased to >1ms ( for example: RC = 100K, 0.1uF)

Partly, no. Because this is under booting up sequence.   My understanding is the SPI boot process will initiated down-side edge of CS_N signal, however CS_N pin is tied to 3.3V line. The actual observed signal I attached.

>> I observed that CS line is driven low which  might be causing the problem. Can you please probe the other SPI lines along with the CS lines and share the traces.

Please let me know if the FX3 clock (either through clock source/ crystal) is stable when the reset is seen.

To narrow down the problem we need to check if the hardware design (except the SPI ) is fine, please try configuring PMODE[2:0] = Z11 (USB boot) and let me know if booting with USB is working fine.

Basically SPI failed case should be transition to USB boot mode, and in this case host PC can recognize as a Cypress device. ( for now , it is not recognized ...) Thus I cannot understand what is going on.

>> To debug the problem please let me know which SPI flash is used in your design. Please refer to this KBA and let me know if the flash is compatible to fx3 Selection of SPI Flash Compatible with FX3/CX3/FX3... - Cypress Developer Community  Please let me know if the issue is seen on multiple boards

Also, confirm is the PMODE[ 2:0] is 0Z1.

Regards,
Rashi

View solution in original post

0 Likes
7 Replies
Rashi_Vatsa
Moderator
Moderator
Moderator
5 likes given 500 solutions authored 1000 replies posted

Hello,

Please confirm if you are aware of the Reset sequence on page 43 of the FX3 datasheet.

Please refer to these KBA for the details Power Up Sequence for FX3 – KBA221826 - Cypress Developer Community 

Power-Up Sequence in FX3™/FX3S – KBA204154 - Cypress Developer Community 

 

where t_rst addressed(when RESET_N will valid)?

>> The Reset should be released only when all the power supplies are stable

when POR ignites?

>> You can check the reset sequence in the datasheet

 after POR, bootloader block works immediately, and loading starts?

>> Yes.

I know in the specification, all of the condition will be set within 1ms, however, real power up time is not set under 1ms. So we should select proper RC value on RESET_N pin.

>> 1ms is the minimum POR time that has to be maintained by the RC circuit. If the other power supplies take more time to stabilize the reset time can be increased by using appropriate RC values

Regards,
Rashi
0 Likes

Hello,

Thank you for the answer.

>>>Reset sequence on page 43 of the FX3 datasheet

The sequence shows VDD is already stabled case, I understood.  My question of this threads are during powering up.

>>> You can check the reset sequence in the datasheet

There are no figures reset sequence in powering up.   My understanding is POR = Power on reset, thus this ignition is only based on voltage (V_TH1?) ... ( then I asked "when" ).  However, RESET_N is set by RC network on pin_5C. and The pin is pulling up with 3V3 powering. (showed in red line in former posted message)   My understanding is bootloader access and SPI access should be start after (RESET_N is asserted + tRR)  by silicon design.  Do you have the information of access time from starting bootloader to SPI access?

However, The timing what I observed is while powering up, the SPI access was occurred that leads fail to load FW correctly. Finally, host PC can not recognize the FX3 device is on the USB line (this was an issue as a consequence). I'd like to understand this phenomena more logically.

I need your advice to understand more.

Thank you,

0 Likes
Rashi_Vatsa
Moderator
Moderator
Moderator
5 likes given 500 solutions authored 1000 replies posted

Hello,

There are no figures reset sequence in powering up

>> No specific power-up sequence for FX3 power domains. Minimum power on reset time of 1 ms should be met and the power domains must be stable for FX3 operation

 My understanding is bootloader access and SPI access should be start after (RESET_N is asserted + tRR)  by silicon design.

>> Yes, the bootloader will start after tRR time of RESET# going high

However, RESET_N is set by RC network on pin_5C. and The pin is pulling up with 3V3 powering. 

>> Please let me know the value of RC and confirm if RESET# pin is pulled to CVDDQ domain. In your case is the CVDDQ is 3.3V?

The timing what I observed is while powering up, the SPI access was occurred that leads fail to load FW correctly.

>> I understand that SPI boot started before RESET# was stabilized to 3.3V. Is that correct? In the figure you shared, the SPI boot start is not clear to me. Please let me know if it started t3/t2

Finally, host PC can not recognize the FX3 device is on the USB line (this was an issue as a consequence)

>> From the PMODE[2:0] lines settings, the bootloader should fall to USB boot when SPI boot fails. Please let me know if that happens. 

For a test please program the SPI flash with bulksrcsink firmware of the SDK and let me know the results.

- Please let me know if PMODE[2:0] can be configured for USB boot (z11) and check if that works fine

- Also refer to this KBA Troubleshooting SPI / I2C Programming in FX3 – KBA... - Cypress Developer Community 

Regards,
Rashi
0 Likes

Hello,

Thank you for your advice.

>>>  In your case is the CVDDQ is 3.3V?
The designed RC=10k, 0.1uF.  Yes, CVDDQ domain is connected to 3.3V system.

>> I understand that SPI boot started before RESET# was stabilized to 3.3V. Is that correct?
Partly, no. Because this is under booting up sequence.   My understanding is the SPI boot process will initiated down-side edge of CS_N signal, however CS_N pin is tied to 3.3V line. The actual observed signal I attached.

fx3_pwr-up_2.png

 

 

 

 

>>> From the PMODE[2:0] lines settings, the bootloader should fall to USB boot when SPI boot fails. Please let me know if that happens. 
Yes, I agree this. Basically SPI failed case should be transition to USB boot mode, and in this case host PC can recognize as a Cypress device. ( for now , it is not recognized ...) Thus I cannot understand what is going on. Perhaps these phenomena are based on internal reset IO of silicon V_TH condition, I guess.. may be wrong?    If you have any ideas let me know please.

Thank you and best,
 
0 Likes

Hello,

The designed RC=10k, 0.1uF.  Yes, CVDDQ domain is connected to 3.3V system.

>> Please let me know if the reset time can be increased to >1ms ( for example: RC = 100K, 0.1uF)

Partly, no. Because this is under booting up sequence.   My understanding is the SPI boot process will initiated down-side edge of CS_N signal, however CS_N pin is tied to 3.3V line. The actual observed signal I attached.

>> I observed that CS line is driven low which  might be causing the problem. Can you please probe the other SPI lines along with the CS lines and share the traces.

Please let me know if the FX3 clock (either through clock source/ crystal) is stable when the reset is seen.

To narrow down the problem we need to check if the hardware design (except the SPI ) is fine, please try configuring PMODE[2:0] = Z11 (USB boot) and let me know if booting with USB is working fine.

Basically SPI failed case should be transition to USB boot mode, and in this case host PC can recognize as a Cypress device. ( for now , it is not recognized ...) Thus I cannot understand what is going on.

>> To debug the problem please let me know which SPI flash is used in your design. Please refer to this KBA and let me know if the flash is compatible to fx3 Selection of SPI Flash Compatible with FX3/CX3/FX3... - Cypress Developer Community  Please let me know if the issue is seen on multiple boards

Also, confirm is the PMODE[ 2:0] is 0Z1.

Regards,
Rashi
0 Likes

Hello,

>>> Please let me know if the reset time can be increased to >1ms ( for example: RC = 100K, 0.1uF)
I tried to use RC=10k,1uF. As a result, it was seems to be OK, because 3.3V, 1.2V, I/O are ready until RESET_N was reached to 3.3V.

>>> I observed that CS line is driven low which  might be causing the problem. Can you please probe the other SPI lines along with the CS lines and share the traces.
Sorry I can't pull out SCLK and MSI, MSO lines by board design. However, I'd like to know why internal reset was released during RESET_N pulling-up... by chance?

>>>Please let me know if the FX3 clock (either through clock source/ crystal) is stable when the reset is seen.
Main CLK (19.2MHz) is synchronized with 3.3V powering. Freq was stable at the CS_N driven timing.

>>>Also, confirm is the PMODE[ 2:0] is 0Z1.
Yes, it was confirmed.

Thanks,

0 Likes

Hello,

I tried to use RC=10k,1uF. As a result, it was seems to be OK, because 3.3V, 1.2V, I/O are ready until RESET_N was reached to 3.3V.

>> Please confirm that with RC = 10k and 1uF, SPI booting was successful. If yes, can you share the traces of power supplies, RESET and SPI CS. Please share the traces with the timings when all the power domains are stabilized and #RESET is asserted

This will help me to understand the issue caused when RC time  = 1ms

Regards,
Rashi
0 Likes