EZ-USB FX3 Read FIFO latency

[JaLo_3720291]

Hi Cypress,

I am working on the EZ-USB FX3 development. The FX3 works as a bridge between the PC and FPGA.

                                   GPIF

     PC > FX3 (slave) >>>>>> FPGA (master)

The GPIF interface used between FX3 and FPGA is based on AN87216. The problem that I am facing is during the SLAVE_RD. According to the application note, the valid data always appears after 2 cycles while the SLRD is low. From the capture below, CLK[221] and SLRD = 0, the valid data should be appeared at CLK[223]. However, the valid data [001F] appeared at CLK[224].

This above case always happens when the SLRD goes from low to high. Any idea?

** I forgot to mention that the watermark is 2.

     CyU3PGpifSocketConfigure(1, CY_U3P_PIB_SOCKET_1, 2, CyFalse, 1);

And, I read the application note AN65974 section 8.3. Did it mean the #SLRD should keep asserted for one more clock cycle (2 x (32/16) - 3) for the data 001f?

Thanks!

Jason