EZ-USB FX3 GPIF-II synchronous master supported clock rates and DLL settings

[AnCo_4758931]

I'm having difficulty figuring out how to get my EZ-USB FX3 GPIF-II synchronous master interface working reliably.

For each of the following questions I only want to know the answers that apply to the EZ-USB FX3 when operating the GPIF-II in synchronous master mode.  I don't care about synchronous slave mode or asynchronous modes.

1. What are the minimum and maximum allowed PCLK frequencies?
2. When executing CyU3PPibInit() what are the minimum and maximum functional clkDiv values for the PibClock?
3. When executing CyU3PPibInit() should isDllEnable be true or false, or does the answer vary based on clkDiv?
4. Do I need to configure the PIB DLL CTRL register (0xE0010028), either directly or via CyU3PPibDllConfigure()?
5. In pib_regs.h the HIGH_FREQ bit includes the comment "0: 23-80MHz, 1:70-230MHz".  Does this mean the PIB DLL CTRL register should only be used for the 23MHz-230MHz frequency range?
6. Various phase selects are defined in pib_regs.h (CORE_PHASE, SYNC_PHASE, OUTPUT_PHASE) and used by CyU3PPibDllConfigure().  Why are these fields not defined in EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. F?

[Rashi_Vatsa]

Hello,

Please refer to this Configuring EZ-USB® FX3™ GPIF-II DLL - KBA210733 - Cypress Developer Community  KBA for details about the GPIF master configuration and answers most of your questions.

2) When executing CyU3PPibInit() what are the minimum and maximum functional clkDiv values for the PibClock?

>> clkdiv is the divider value for the PIB clock. The min value is 2 and max value is 1024 but the minimum supported PCLK (external) for synchronous GPIF is 10 MHz according to the KBA

[AnCo_4758931]

I'm familiar with KBA210733.  It is out-of-date and incorrect when compared to the comments in pib_regs.h and has not been updated to reflect the PIB DLL functionality added in SDK 1.3.4.  For example, KBA210733 recommends setting DLL mode to Slave when the frequency is less than 80MHz, but according to pib_regs.h it should never be set to Slave during normal operation:

/*
   DLL Operation mode for the PIB master DLL. This field is used only for
   DLL characterization. During normal operation the only allowed value for
   this field is "0".
     0: DLL is master mode. The DLL locks to its input clock
     1: DLL is in slave mode. The DLL creates delays based on the values
   specified in DLL_SLAVE_DLY register field
 */

It's also worth pointing out that several of the fields referenced in KBA210733 (including that Mode bit) aren't documented in the Technical Reference Manual.  KBA210733 also doesn't answer any of my posted questions.

[Rashi_Vatsa · Accepted solution]

Hello,

Please refer to cyu3pib.h file which mentions that the normal mode is the DLL master mode 

" When operating in the normal (master) mode, the DLL block has limitations with respect to the minimum interface clock frequency (80MHz) that can be supported.

For lower frequency interfacing clock, CYU3P_PIB_DLL_SLAVE should be used which will use the slave delay (SLAVE_DELAY) as per user programmed fixed delay value.

1. What are the minimum and maximum allowed PCLK frequencies?

>> The supported interface clock range  for synchronous mode is from 10 MHz to 100 MHz

3. When executing CyU3PPibInit() should isDllEnable be true or false, or does the answer vary based on clkDiv?

>> You can call CyU3PPibInit() with isDllEnable = CyFalse and then call CyU3PPibDllConfigure() as the in implementation of CyU3PPibDllConfigure() the steps mentioned in section 2.1 of the KBA are followed i.e. the DLL will be disabled first and then PIB_DLL_CTRL is configured 

4. Do I need to configure the PIB DLL CTRL register (0xE0010028), either directly or via CyU3PPibDllConfigure()?

>> CyU3PPibDllConfigure can be used for configuring the PIB_DLL_CTRL. You can refer to SramMaster example of the FX3 SDK which configures the DLL for asynchronous mode using CyU3PPibDllConfigure 

5. In pib_regs.h the HIGH_FREQ bit includes the comment "0: 23-80MHz, 1:70-230MHz".  Does this mean the PIB DLL CTRL register should only be used for the 23MHz-230MHz frequency range?

>> This frequency is not the PCLK (GPIF interfacing clock frequency). You can configure this parameter as per Table 2 of the KBA

It's also worth pointing out that several of the fields referenced in KBA210733 (including that Mode bit) aren't documented in the Technical Reference Manual. 

>> Thank you for the suggestion. I will forward this to the concerned team.

Please let me know if more queries are there