I am using cypress FX3 GPIF II slave fifo interface in my design. I am trying use dual Sockets seamless transfers with single EP's (both EP1 IN and EP2 OUT). 2bit address slave fifo mode.
1) Whether Socket 0 (thread0) and Socket 1 (thread1) i.e multiple sockets can able push data to PC through single End point (EP1 IN)
2) Similarly can Socket 2 (thread2) and Socket 3 (thread3) can able to fetch data from PC through single End point (EP2 OUT)
Basic question is Single End point can be used with two sockets (dual Sockets seamless transfers)? or else in order to perform dual sockets transfers it required to use two EP's.
If this is possible can you please point me any example design which use two sockets with single EP's (many to one) scheme.?
Both the requirements are possible. Please refer the examples in "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\dma_examples\cyfxbulklpmanonetomany" and "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\dma_examples\cyfxbulklpmanmanytoone"
In these examples data sent through an out endpoint and be read back by two In EndPoints and vice versa. The DMA Channels in each of these firmwares are of the type MANUAL_ONE_TO_MANY and MANUAL_MANY_TO_ONE.
However, these firmware have not implemented the GPIF Interface, But it is possile in GPIF Interface also. You can our video camera example in An75779 application note. Where the GPIF Sockets 0 and 1 are used to receive video data and it is sent out of FX3 using 0x83 endpoint. There are many things to be considered in implementing this. Please contact tech support for more details.
- Madhu Sudhan
Thanks for Quick reply.
I got your point that data sent through an out endpoint and can be read back by two In EndPoints and vice versa. But still i am having one more doubt,
If data sent through an one out endpoint and be read back by one In EndPoint. In this case whether i can use multiple threads/sockets for each end point to communicate with External side.
For example if data read for one In End point and communicated to External processor/FPGA via two threads/sockets instead of one thread/socket and viceversa. According to documents its mentioned as each socket represents each end point in USB side.