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USB Superspeed Peripherals

MaXi_1246331
Contributor

Some days ago, I prompt a question (partial flags of FX3 ) on partial flags of FX3. It has not been solved.

Today I find I document it can answer my question. The document says a bug exist in partial flag of out endpoint of FX3. The described phenomenon is pretty much like what I have experienced. The only difference is my test shows the partial flag get right after the host sent data to FX3, not the master read data from FX3 as described in the doc. In my test, I let the master do nothing and keep the nCS(chip select), nOE, nRD, nWR, packet end pins of Slave FIFO interface de-asserted.

Was the content of this document true? Does the described problem still exist for newly produced FX3?

Thank you.

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1 Solution
alamandaa_16
Moderator
Moderator

Hello,

It looks similar what you observed in your case and documented.

Can you please let us know how did you come to this point - "The only difference is my test shows the partial flag get right after the host sent data to FX3, not the master read data from FX3 as described in the doc".

The flags behaves same irrespective of master reading the data or Host sent the data to FX3 (USB -> GPIF).

Above attached document confusion created in Flag status( asserted and deasserted) ,we did flag status corrections please see the attached document.

Was the content of this document true?

The content of document is true.

Does the described problem still exist for newly produced FX3?

Yes, problem still exist.

Regards,

Anil Srinivas.

View solution in original post

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4 Replies
abhinavg_21
Moderator
Moderator

Hi Marverick,

We haven't made any change in the FX3 silicon and hence still you can't rely on watermark flags for start sending the data. It is advised to make use of DMA Ready flag before start sending data.

Thanks & Regards

Abhinav

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alamandaa_16
Moderator
Moderator

Hello,

It looks similar what you observed in your case and documented.

Can you please let us know how did you come to this point - "The only difference is my test shows the partial flag get right after the host sent data to FX3, not the master read data from FX3 as described in the doc".

The flags behaves same irrespective of master reading the data or Host sent the data to FX3 (USB -> GPIF).

Above attached document confusion created in Flag status( asserted and deasserted) ,we did flag status corrections please see the attached document.

Was the content of this document true?

The content of document is true.

Does the described problem still exist for newly produced FX3?

Yes, problem still exist.

Regards,

Anil Srinivas.

View solution in original post

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MaXi_1246331
Contributor

My host code is like these:

Host send 10 bytes to out endpoint

Host clear this endpoint.

Host Send 100 bytes to out endpoint

Host clear this endpoint.

Host send 10 bytes to out endpoint

Host clear this endpoint.

Host Send 100 bytes to out endpoint

Host clear this endpoint.

The water mark is set to 4 4-byte words(16 bytes). I choose low active and init low for this partial flag. master FPGA do not read any data from FX3. Host computer communicate with FX3.

The following is the partial flag responses.

1 Host send 10 bytes to out endpoint

then, partial flag transit from high to low.

2 Host clear this endpoint.

then, partial flag keeps low.

3 Host Send 100 bytes to out endpoint

then, partial flag transit from low to high.

4 Host clear this endpoint.

then, partial flag keeps high.

5 Host send 10 bytes to out endpoint

then, partial flag transit from high to low.

6 Host clear this endpoint.

then, partial flag keeps low.

7 Host Send 100 bytes to out endpoint

then, partial flag transit from low to high.

8 Host clear this endpoint.

then, partial flag keeps high.

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MaXi_1246331
Contributor

aani​ I do not see your attached file. Thank you.

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