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USB Superspeed Peripherals

AvOm_4629506
New Contributor II

Good day, gentlemen and ladies. I have a problem with USB3 on CX3. I used CyU3PUsbInitEventLog and CyU3PUsbGetEventLogIndex to understand why USB 3 is being disabled and this is what I got:

0x6 CYU3P_USB_LOG_USB3_PHY_ON Indicates that the 3.0 PHY has been turned on

0x10 CYU3P_USB_LOG_USBSS_DISCONNECT Indicates that the USB 3.0 link has been disabled

0x4 CYU3P_USB_LOG_USB3_PHY_OFF Indicates that the 3.0 PHY has been turned off

0x5 CYU3P_USB_LOG_USB2_PHY_ON  Indicates that the 2.0 PHY has been turned on

0x40 CYU3P_USB_LOG_USB2_SUSP  Indicates that a USB 2.0 suspend condition has been detected

0x41 CYU3P_USB_LOG_USB2_RESET Indicates that a USB 2.0 bus reset has been detected

0x51 CYU3P_USB_LOG_USBSS_ENABLE Indicates that a USB 3.0 connection is being attempted again

0x42 CYU3P_USB_LOG_USB2_HSGRANT Indicates that the USB High-Speed handshake has been completed

0x10 CYU3P_USB_LOG_USBSS_DISCONNECT Indicates that the USB 3.0 link has been disabled

0x46 CYU3P_USB_LOG_USB2_SETCONF Indicates that USB configuration has been selected

0x40 CYU3P_USB_LOG_USB2_SUSP  Indicates that a USB 2.0 suspend condition has been detected

0x41 CYU3P_USB_LOG_USB2_RESET Indicates that a USB 2.0 bus reset has been detected

0x51 CYU3P_USB_LOG_USBSS_ENABLE Indicates that a USB 3.0 connection is being attempted again

0x42 CYU3P_USB_LOG_USB2_HSGRANT Indicates that the USB High-Speed handshake has been completed

0x10 CYU3P_USB_LOG_USBSS_DISCONNECT Indicates that the USB 3.0 link has been disabled

0x46 CYU3P_USB_LOG_USB2_SETCONF Indicates that USB configuration has been selected

what can this be related to?

I use exactly the USB 3 Port since I have USB 3 devices and they connect to it normally

#ifdef UVC_APPLICATION

/* Standard Device Descriptor for USB 3 */

const uint8_t CyCx3USB30DeviceDscr[] =

{ 0x12, /* Descriptor size */

CY_U3P_USB_DEVICE_DESCR, /* Device descriptor type */

0x00, 0x03, /* USB 3.0 */

0xEF, /* Device class */

0x02, /* Device Sub-class */

0x01, /* Device protocol */

0x09, /* Maxpacket size for EP0 : 2^9 */

0xB4, 0x04, /* Vendor ID */

0xC3, 0x00, /* Product ID */

0x00, 0x00, /* Device release number */

0x01, /* Manufacture string index */

0x02, /* Product string index */

0x00, /* Serial number string index */

0x01 /* Number of configurations */

};

/* Standard Device Descriptor for USB 2 */

const uint8_t CyCx3USB20DeviceDscr[] =

{ 0x12, /* Descriptor size */

CY_U3P_USB_DEVICE_DESCR, /* Device descriptor type */

0x10, 0x02, /* USB 2.1 */

0xEF, /* Device class */

0x02, /* Device sub-class */

0x01, /* Device protocol */

0x40, /* Maxpacket size for EP0 : 64 bytes */

0xB4, 0x04, /* Vendor ID */

0xC3, 0x00, /* Product ID */

0x00, 0x00, /* Device release number */

0x01, /* Manufacture string index */

0x02, /* Product string index */

0x00, /* Serial number string index */

0x01 /* Number of configurations */

};

/* Binary Device Object Store (BOS) Descriptor */

const uint8_t CyCx3USBBOSDscr[] =

{ 0x05, /* Descriptor size */

CY_U3P_BOS_DESCR, /* Device descriptor type */

0x16, 0x00, /* Length of this descriptor and all sub descriptors */

0x02, /* Number of device capability descriptors */

/* USB 2.0 Extension */

0x07, /* Descriptor size */

CY_U3P_DEVICE_CAPB_DESCR, /* Device capability type descriptor */

CY_U3P_USB2_EXTN_CAPB_TYPE, /* USB 2.1 extension capability type */

0x02, 0x00, 0x00, 0x00, /* Supported device level features - LPM support */

/* SuperSpeed Device Capability */

0x0A, /* Descriptor size */

CY_U3P_DEVICE_CAPB_DESCR, /* Device capability type descriptor */

CY_U3P_SS_USB_CAPB_TYPE, /* SuperSpeed device capability type */

0x00, /* Supported device level features  */

0x0C, 0x00,//0x0E, 0x00, /* Speeds supported by the device : SS, HS and FS */

0x02, /* Functionality support */

0x0A,//0x00, /* U1 device exit latency */

0xFF,0x07//0x00, 0x00 /* U2 device exit latency */

};

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1 Solution
AvOm_4629506
New Contributor II

URAAAA Comrades!

USB3 is up !!

it was all about a dead RCLAMP0524J (D14 on the circuit).

Thank you very much for your help

View solution in original post

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14 Replies
YashwantK_46
Moderator
Moderator

Hello,

Can you please let me know the following details:

1.) What is the SDK version you are using?

2.) What OS are you using and which architecture is it(32-bit or 64-bit)?

3.) Which USB 3.0 host controller are you using?
4.) Is it a CX3 Denebola RDK or your custom board?

5.) Can you please try using USBBulkSrcSink example firmware from the SDK and see if the device is enumerating as a 2.0 device or 3.0 device?

Also, can you please confirm if you are using CyU3PConnectState (CyTrue, CyTrue); to enable the SS USB PHY in CX3?

Regards,
Yashwant

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AvOm_4629506
New Contributor II

Hi

1. 1.3.4

2. Linux Ubuntu 19.10 64bit

3. xHCI Host Controller Manufacturer: Linux 5.3.0-46-lowlatency xhci-hcd

Host <---DN/DP----> USBLC6-2SC6 (protect)  -------------------------> CYUSB3065-BZXI

        <---SSTX_N/P, SSRX_N/P ----> rclamp0524j.tct (protect)---->  ^                                      

4. custom board

5. compiled and uploaded the cyfxbulksrcsink project from the SDK to CX3

pastedImage_1.png

USB2.1

CyU3PConnectState (CyTrue, CyTrue); - Yes I use it

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YashwantK_46
Moderator
Moderator

Hello,

Thank you for the confirmation.

Can you please try testing USBBulkSrcSink example on different host PC's and with different OS and see if the issue persists?
Also, if you have multiple custom boards, can you try to test all of them to see if they are behaving similarly?

This would help isolate the problem to either the host side or the hardware side.

Regards,

Yashwant

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AvOm_4629506
New Contributor II

Thank you for responding to the call

Tested on 2 systems on Linux Mint 64 and win 10 (64)... everywhere USB2. 1

pastedImage_2.jpg

I found this text:

"With USB 3.0, a separate SuperSpeed USB channel co-exists in parallel with the normal USB 2.0 bus. It is important to point out that SuperSpeed USB is a full-duplex bus, thus both the host and the device act as a transmitter and receiver. In order to communicate over USB 3.0, each transmitter must detect the termination on the receiver side. If the termination is not detected, the host will downgrade its communications to USB 2.0. If the termination is detected, link training begins so that the receiver can synchronize with the transmitter. Once the link is established, the link enters U0 and data communications can begin."

I understand correctly that the terminal resistor is in CX3 ? Can I check it somehow?

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YashwantK_46
Moderator
Moderator

Hello,

There USB terminations are handled by the USB PHY inside CX3 and these can't be checked.

Since the behaviour is same in different host PC's as well as different OS's and the default firmware too, this most likely is an issue with the hardware.


Please refer to the following KBA and make sure your custom board complies with it: USB 3.0 Device Enumerated as USB 2.0 – KBA204163

Regards,
Yashwant

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AvOm_4629506
New Contributor II

Good afternoon.

Now I looked at what is happening on the SSTXP/SSTXN line and at the moment of switching on received the following waveform:

pastedImage_2.png

and the next one relative to earth

pastedImage_3.png

Are these waveforms correct?

On the U3RXVDDQ and U3TXVDDQ power lines V = 1.2 Vp = 32mV. In https://community.cypress.com/docs/DOC-16768 written noise less than 20mV is from peak to peak ? Vp = 32mV is peak to peak

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YashwantK_46
Moderator
Moderator

Hello,

The 20mV noise level mentioned in the KBA is from peak-to-peak and it should be made sure that the noise on power supplies AVDD, U3TX_VDDQ, and U3RX_VDDQ should be below 20 mV and  on VDD should be below 100 mV.

I am unable to comment correctly about the waveforms as of now.

Can you please share you schematics for me to review so that we can see if the hardware is correctly according to recommendations?

Regards,
Yashwant

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AvOm_4629506
New Contributor II

Good day.

Here are the schematics. interference on U3RXVDDQ, U3TXVDDQ measured on capacitors C39, C43.

IMG_20200622_094947.jpg

IMG_20200622_095110.jpg

Here is another image of the moment when I connect USB 3 to the Board. There you can see a short impulse, and then a second one with a very long decline. I look between GND-DRAIN and SSTX on the xs23 connector

img.jpeg

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YashwantK_46
Moderator
Moderator

Hello,

Thanks for those images but would it be possible for you to share the schematics file as a pdf?

Its hard to review the schematics from the images.
Please share the complete schematics in pdf format so that i can review them better and get back to you with my comments.


Regards,

Yashwant

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AvOm_4629506
New Contributor II

Good afternoon.

To reduce noise from the power source, the Board is powered by a battery, but still does not want to be defined as USB 3.

now we have removed the ID-GND jumper from the USB3 mini type B connector , so now the ID leg is hanging in the air

USB EVENT LOG:

0x6

0x10

0x4

0x5

0x40

0x41

0x51

0x42

0x10

0x41

0x51

0x42

0x10

0x46

0x40

0x41

0x51

0x42

0x10

0x41

0x51

0x42

0x10

0x46

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YashwantK_46
Moderator
Moderator

Hello,

The attached USB log in the latest response looks similar to the log in the first interaction.

The ID pin can be left unconnected.


Please go through the AN70707 hardware design guidelines from the link: https://www.cypress.com/file/139936/download

Please find my comments below after reviewing the schematics:

1.) There needs to be a 22uF bulk capacitor on the VDD domain (Only 14.5uF combined capacitance present in schematic).

2.) VDD_MIPI can also be tied to the VDD capacitor bank instead of using separate capacitors for it.

3.) The recommended capacitors on U3RXVDDQ and U3TXVDDQ are 22uF and 0.1uF in parallel.

4.) The VDDIO1,2,3 should have the de-caps as shown in the below image:

pastedImage_3.png


Regards,
Yashwant

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AvOm_4629506
New Contributor II

Good afternoon.

added capacitors, but the result is still USB2 instead of USB3. we will dig further... or replace the processor

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YashwantK_46
Moderator
Moderator

Hello,

Please refer to the AN70707 app note and make sure that the design, both the schematics and layout, pass through the Schematic and Layout Checklist provided in Table 11 on Page 28 and 29.

The link for the app note is as follows: https://www.cypress.com/file/139936/download

Regards,
Yashwant

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AvOm_4629506
New Contributor II

URAAAA Comrades!

USB3 is up !!

it was all about a dead RCLAMP0524J (D14 on the circuit).

Thank you very much for your help

View solution in original post

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