Dealing with transitory Synchronous Slave FIFO Overruns

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Anonymous
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     What would be a reasonable way to detect transitory buffer overruns without using external hardware configured as a synchronous slave FIFO connected directly to an external imager?.   
   
         
   
     I would like to interface an external imager to the FX3 without any external hardware. The general timings of the imager satisfies the interface requirements of the synchronous slave FIFO configuration.      
   
         
   
     I can configure the size of the ram buffers to be evenly divisible the imager line size ensuring the transition between buffers only occurs during line idle time.  However, I need to handle the error case where all of the buffers are full when the imager begins to write the next line into the buffer. The occurrence of FIFO FULL, WRN, and CLK may be transitory. The worst case for detection would be a one CLK overlap between the FIFO FULL flag and WRN.    
   
         
   
     I can add external hardware to detect this case if necessary. However, it would seem reasonable that the FX3 would have the ability to detect this occurrence or deal with the situation w/o requiring external hardware. Is there a way to detect this error occurrence using only the facilities of the FX3?   
   
         
   
     Thanks,   
   
     Bob   
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3 Replies
Anonymous
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You should be able to use DMA_RDY_CT i.e. this signal says whether the DMA is ready to receive or send data. If a transfer is tried when it is not true i.e. the DMA is not ready you can use that to find out the overflow, underflow condition.

   

Regards,

   

Anand

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Anonymous
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I cannot find the symbol DMA_RDY_CT. I searched all the .c and .h files within the directory where I installed the Cypress SDK and didn't find it.

   

The condition of the FIFO FULL and my attempting to write into the buffer may only occur very briefly on the interface. Will this flag latch that occurrance? IE: will it remain TRUE after the physical occurrence has gone away?

   

Can I use this occurrance to generate an interrupt?

   

Bob

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Anonymous
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This answer was verified unintentionally. I have opened a tech support case to elevate this issue.

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