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USB Superspeed Peripherals

poas_4520791
New Contributor II

Hi,

I'm transfering data from FX3 to FPGA and the interface i'm using is GPIF II.

Based on AN65974  GPIF II files i have created a state machine and modified interface settings according to it.Now i'm using two flags(active low signals)  flagC(DMA_READY) and flag D(watermark flag).Through Control Center i'm transfering the data to FPGA ,but the data i'm receiving  on FPGA side is 0000 and here the flags are initially 1(low) and after programming flag C is 0(high) and flagD is 1. If flagC is 0 means the buffer is having some data but i'm not able to receive data on FPGA side.

Kindly,anyone let me know the reason for this issue.

Regards,

Aswini

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1 Solution
JayakrishnaT_76
Moderator
Moderator

Hello,

The change of flag signals are as expected. At first the ready flag is low. Then when the data transfer is done, it changes to HIGH. This indicates that there is some data in the FIFO to be read. Now you need to use FPGA to assert SLRD and SLOE signals according to fig 3 of AN65974. For ending the transfer you need to monitor the watermark flag. Make sure that at the start of the transfer you do not monitor the watermark flag as it shows a different behaviour.

I think this thread is a continuation of FX3 to DDR3

Please update the results in the previous thread itself.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna

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1 Reply
JayakrishnaT_76
Moderator
Moderator

Hello,

The change of flag signals are as expected. At first the ready flag is low. Then when the data transfer is done, it changes to HIGH. This indicates that there is some data in the FIFO to be read. Now you need to use FPGA to assert SLRD and SLOE signals according to fig 3 of AN65974. For ending the transfer you need to monitor the watermark flag. Make sure that at the start of the transfer you do not monitor the watermark flag as it shows a different behaviour.

I think this thread is a continuation of FX3 to DDR3

Please update the results in the previous thread itself.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna

View solution in original post

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