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Using the GPIF_DESIGNER, inside the same state, I drive an early mode control (DR_GPIO) and also data (DR_DATA).
According to what I understood from the Cypress documentation, the control has a 2-clock latency while data is driven right away. So, control is reaching the FPGA interface 2 clocks later than the moment state was active and also 2 clocks after data reaches the FPGA interface.
We could not see this by actual measurement. Actually both the control and data come at the same time. I believe documentation should have details about relative timing between controls and data.
I will appreciate clarifications on this. The system is synchronous (PCLK used), GPIF II on 32 bits and driving data while a control (WE) is asserted needs to be precisely controlled.