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Hi i would lie to rest all the DMA Flag doubts that has been a bother for a while.
- For writing to Slave Fifo ie FPGA to GPIF
A current thread DMA RDY flag shows logic high or logic low (when the Buffer is Full/Not Full) ?
- For reading from Slave Fifo ie GPIF to FPGA
A current thread DMA RDY flag shows logic high or logic low (when the Buffer is Empty/NotEmpty)?
Now regarding partial flags..
- Can we use the partial flag to check the to- be- written GPIF socket( by FPGA) . If it is not asserted we can judge that there must be space to be written ..right?? is it essential that we need a DMA ready flag for starting a transfer..
"DMA_RDY" is actually a signal that is asserted when there is no DMA buffer available to satisfy the request."
Is this a valid conclusion .
utmost curiosity
Denny
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Hi,
For FPGA to GPIF (SlaveWrite):
If flag is asserted, DMA Buffers are full inside FX3. So FPGA cannto write. If flag is de-asserted, write can be done.
(Asserted means High if Flag is Active high. Asserted means Low if flag is active low)
For GPIF to FPGA (SlaveRead):
If flag is asserted, DMA Buffers are empty inside FX3. So FPGA cannot read. If flag is de-asserted, readcan be done.
(Asserted means High if Flag is Active high. Asserted means Low if flag is active low)
Your assumption that "DMA_RDY" is actually a signal that is asserted when there is no DMA buffer available to satisfy the request." is valid
Regarding Partial Flags:
For FPGA to GPIF: You can actually monitor the partial flag for starting the transfer (provided you call the CyU3PSMStart API after the DMA Channel is created and started (CyU3PDmaChannelCreate and CyU3PDmaChannelSetXfer)
For GPIF to FPGA: There is a bug in Fx3 which makes it not possible to monitor the partial flag for beginning slave read. There is a dirty workaound for using partial flags alone. We recommend you to this workaround, only if are running short of pins and must avoid using the DMA Ready flag for starting the transfer, If, so please let us know. We will provide you the steps for the workaround for using the partial flag for starting the data transfer.
If not, if you are OK with monitorng the DMA Ready flags for starting the data transfer, please proceed with it.
Regards,
-Madhu Sudhan
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Hi Madhu,
could you please provide this workaround, because due to lag of pins, we would like to use partial flags only instead of using both the full/empty and the partial flags.
Regards
Stefan
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Hi Stephen,
Please refer the attached doc for details and workaround.
Regards,
- Madhu Sudhan
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Hi Madhu.
This is a great piece of info. Thanks for saving a lot of time and pins..
Denny
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Hi Madhu.
Thank you for this information.
Just a question for clarification:
In the document there is a signal flow of the DMA_ready and the DMA_Watermark flag (p. 2). For event "B" it denotes that the DMA_ready flag (green signal) is "de-asserted". I'm not sure but I think here the DMA-ready flag is still "asserted", only the DMA_Watermark flag (red signal) is de-asserted.
Is my observation correct?
Regards,
Stefan
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Yes, You are right. That was a typo
regards,
- Madhu Sudhan
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Hai Madhu sir,
Thanks for giving a Partial flag information work around condtion.
Q1. The code is given, is only one time initiation or I have to push dummy data in every time?.
Q2. I need more information about work around condition of state machine.
Thank you.
Best Regards,
Thrimurthi M
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Hi Thrimurthi,
You have to push the dummy data only one time when the DMA channel is created. But I am not sure whether you have to push dummy data after resetting the DMA channel. Please probe the DMA Water MARK flag and verify its state once the DMA channel is resetted.
Thanks & Regards
Abhinav
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Hai Madhu sir,
The Given Wave form diagram in Flag.doc only at 1st sample Partial flag is de-asserted before the data in buffer, then it is going good but in my case all the sample period partial flag taking same period . it asserted de-before the data in buffer.
In figure what A to G is there same action is repeated sequentially. I am not getting G to F.
Q1. Is any problem in my firmware? am using slave FIFO example.
Thank you.
with best Regards,
Thrimurthi M