DMA Watermark flag

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MaMa_4520856
Level 4
Level 4
25 replies posted 25 sign-ins 10 replies posted

Hello,

I've got problem with DMA watermark flag for write transfer. From the very beginning it is in it's initial state (active low and initial low), when as per my understanding it should go to low state after I fill buffer with some data. Could it be I have to adjust watermark value in my firmware? Below I attach screen from chip scope.

My FPGA is monitoring state of that flag and when it's changes it state to low allows to write few more words to Fx3 device (based on watermark value in my case watermark is 3)

I've double check my FPGA is monitoring right port (flag uses GPIO21 witch is CTL4 signal in Fx3, G25 in interconnection board).

state machine I use: SyncADMUx(16bit data bus 7bit address bus)

firmware: slave fifo (AN65974; with 2 isochronus endpoint)

I use xilinx FPGA (SP605), and cypress cyusb3-001 kit.

Regards,

Mateusz

 

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Hello Rashi,

When I swapped flags B and C in gpif designer and source of those flags in VHDL code, now Flag C stays in low no matter if I send any data to Fx3 and flag B is in high state as it should be. So I understand there is some problem with that path in Interconnection board and I should avoid it by not using GPIO21 pin

Regards,

Mateusz

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