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USB Superspeed Peripherals

MaMa_4520856
New Contributor II

Hello,

I've got problem with DMA watermark flag for write transfer. From the very beginning it is in it's initial state (active low and initial low), when as per my understanding it should go to low state after I fill buffer with some data. Could it be I have to adjust watermark value in my firmware? Below I attach screen from chip scope.

My FPGA is monitoring state of that flag and when it's changes it state to low allows to write few more words to Fx3 device (based on watermark value in my case watermark is 3)

I've double check my FPGA is monitoring right port (flag uses GPIO21 witch is CTL4 signal in Fx3, G25 in interconnection board).

state machine I use: SyncADMUx(16bit data bus 7bit address bus)

firmware: slave fifo (AN65974; with 2 isochronus endpoint)

I use xilinx FPGA (SP605), and cypress cyusb3-001 kit.

Regards,

Mateusz

 

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1 Solution
MaMa_4520856
New Contributor II

Hello Rashi,

When I swapped flags B and C in gpif designer and source of those flags in VHDL code, now Flag C stays in low no matter if I send any data to Fx3 and flag B is in high state as it should be. So I understand there is some problem with that path in Interconnection board and I should avoid it by not using GPIO21 pin

Regards,

Mateusz

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9 Replies
Rashi_Vatsa
Moderator
Moderator

Hello Mateusz,

For writing to FX3 Slave FIFO interface, following the formula for configuring the partial flag

The number of data words that may be written after the clock edge at which the partial flag is sampled low = watermark x (32/bus width) – 4.

In your case, as watermark value is 3 and bus width is 16, FPGA should write 2 data words after the watermark flag is sampled low.

 Could it be I have to adjust watermark value in my firmware? 

>> Please let me know if the watermark fag is configured as 3 using CyU3PGpifSocketConfigure API. The third parameter of this API will set the watermark value.

Could you please share the GPIF state machine (.cyfx) file for us to check.

 From the very beginning it is in it's initial state (active low and initial low), when as per my understanding it should go to low state after I fill buffer with some data

>> Please let me know which flag is DMA watermark flag in the traces. If the initial state of the flag is low, the FLAG will be low initially when the transfers are not started. 

Regards,
Rashi
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MaMa_4520856
New Contributor II

Hello Rashi ,

Sorry for not clear massage. Here is how I use watermark values:

CyU3PGpifSocketConfigure (0,CY_U3P_PIB_SOCKET_0,3,CyFalse,1);
CyU3PGpifSocketConfigure (3,CY_U3P_PIB_SOCKET_3,3,CyFalse,1);

It's about flag B (on my screenshot just B), flag A and C are DMA Ready, B and D partial flag, flag D works as expected, after it goes low few moments later flag C also goes low saying that buffer is empty.

I'm sending whole folder with gpif state machine.

Regards,

Mateusz

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Rashi_Vatsa
Moderator
Moderator

Hello Mateusz,

Please let me know how is the data transfer started from the Master side.

Please let me know if the data transfer (write to FX3) can be started based on the DMA Ready flag and stopped after monitoring the DMA Watermark flag. Please let me know if this works.

Please let me know if FLAB B (watermark) flag goes HIGH from initial state (LOW) once some data is written to FX3.

Regards,
Rashi
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MaMa_4520856
New Contributor II

Hello Rashi,

Basically I try to do the loopback, I transfer data using USB Control Center (provided with Ez-USB Suite), the Master device monitor flag C and D if both are high, then I setup Slave device for read transfer (address line is 3) and wait for RDY signal from slave device. Once RDY is high I store data that I'm reading to RAM. After flag D goes low, I read only few more words then end transfer by setting both OE and CE high. If flag A is high then I setup Slave device for write transfer (address line is 0), wait for RDY to be HIGH and then I start writing data that I stored in read cycle.

I'll write a tast case only for write transfer and see if FLAG B will change to HIGH. I'll send another reply when I finish.

Regards,

Mateusz

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MaMa_4520856
New Contributor II

Write transfer waits only for flag A (DMA_READY) to goes high and based on watermark  flag (B) is ending.

The WE signal is asserted after flag A goes high and data are being written after rdy signal goes high.

The flag B stays low even when I write some data to Fx3 

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Rashi_Vatsa
Moderator
Moderator

Hello Mateusz,

Please confirm if the FX3 is programmed first and then the FPGA is configured.

Kindly let me know the status of Flag B (GPIO[21] -  using oscilloscope) when FPGA is not connected to FX3 and FX3 is programmed with the firmware.

Regards,
Rashi
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MaMa_4520856
New Contributor II

Hello Rashi,

First I programm Fx3, then configuring FPGA.

I don't have osciloscop, I can try to route signal to a diffrent GPIO pin (i.e swap flag C and B, I know that flag C is working properly).

 

Regards

Mateusz

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Rashi_Vatsa
Moderator
Moderator

Hello Mateusz,

I don't have osciloscop, I can try to route signal to a diffrent GPIO pin (i.e swap flag C and B, I know that flag C is working properly).

>> Yes, this can be done. With this we can understand if the problem is not due to the routing. 

If you do not have oscilloscope, could you check the voltage on GPIO[21] of FX3 (when Flag B is routed to GPIO[21])?

Regards,
Rashi
MaMa_4520856
New Contributor II

Hello Rashi,

When I swapped flags B and C in gpif designer and source of those flags in VHDL code, now Flag C stays in low no matter if I send any data to Fx3 and flag B is in high state as it should be. So I understand there is some problem with that path in Interconnection board and I should avoid it by not using GPIO21 pin

Regards,

Mateusz

View solution in original post

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