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USB Superspeed Peripherals

prateekmohan
New Contributor

Hello,

I am interested in using the Cypress FX3 as a mechanism to communicate with our FPGA. I basically need a method for two communication platforms:

1. FPGA will stream data out to an ARM processor connected via USB (through the Cypress FX3) 

2. ARM processor needs to be able to read some registers (BRAM) on the FPGA through the same USB link and be able to set some registers (BRAM) to dictate what the FPGA will stream out. 

I am following the information in the document AN65974 - Designing with the EZ-USB® FX3™ Slave FIFO Interface (cypress.com) and I can see that there is a pathway for me to do #1. The "FX3 Slave interface" described in an example like below seems to be a way of me to transfer data out of the FPGA using the "EP1_IN" interface. 

prateekmohan_0-1618004761799.png

However, what I am wondering is how to implement #2 - it is certainly possible to do it via some sort of opcode based protocol using EP1_OUT but what I risk doing in that respect is now data in EP1_IN is containing different streams of input data sources that need to be multiplexed in the USB Host (the ARM Core).

Is there perhaps a more elegant solution to do what I am describing? I saw that there is capability for an I2C and SPI interface on the FX3, but I am not too sure what this refers to. Does this appear like a SPI or I2C interface to the FPGA? Something like that could work - so the I2C/SPI interface is used as my #2 requirement.

Thanks for the help!

Prateek

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3 Replies
AliAsgar
Moderator
Moderator

Hi Prateek,

From your post, what I have understood is, there is an ARM Core which is the USB Host in your application. The ARM Core and the FPGA need to communicate with each other via FX3. Is my understanding correct?

If this is the case, SPI/I2C interface can be used to read/write from FX3 > FPGA. FX3 can act as SPI/I2C Master.

Also could you explain exactly what is the risk being talked about here,  "what I risk doing in that respect is now data in EP1_IN is containing different streams of input data sources that need to be multiplexed in the USB Host (the ARM Core)."

Best Regards,
AliAsgar

 

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prateekmohan
New Contributor

Hey Ali, 

Thanks for the quick reply! I have my comments below:

"The ARM Core and the FPGA need to communicate with each other via FX3. Is my understanding correct?"

Yes this is correct, that's what I want to do. 

My statement: "what I risk doing in that respect is now data in EP1_IN is containing different streams of input data sources that need to be multiplexed in the USB Host (the ARM Core)."

I should explain a little bit more. The ARM core's data transfer to/from the FPGA falls into three buckets:

1. Data coming from the FPGA to the ARM core with high speed data rate. This is for sensor data, and the ARM core will be reading data very quickly so the method I mentioned in the image using the EP1N socket works.

2. Data going from ARM core to FPGA. This is for control commands, and will be going into a register based interface on the FPGA. This does not need to be as fast, so I am thinking of using the FX3 as a SPI/I2C master. So the ARM would issue I2C/SPI transactions, and the relevant GPIOs (for SPI/I2C) out of the FX3 will be connected to the FPGA.

3. Data going from FPGA to ARM core with low data rate. This is if the ARM core needs to read data from registers on the FPGA. This data stream does not need to be that fast, so I also wanted to use the I2C/SPI interface I mentioned in #2 to perform this. 

What I was unsure about is how the data for #3 comes back to the USB Host (ARM Core). Does it also go through the same EP1_IN interface? That was what I meant about a risk - there would be two different sources of data going back to the ARM core (data from #1, and data from #3). How does this get shown on the ARM Core? Or is it abstracted away from it on the USB Host? I guess what I really mean is if I use the "CyU3PI2cTransmitBytes" to transmit bytes, does it also go through the EP1_OUT in my diagram? And if I use the "CyU3PI2cReceiveBytes", does it go through the EP1_IN in my diagram?

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AliAsgar
Moderator
Moderator

Hi Prateek,

For the #3, when the data is sent to FX3 from FPGA using the I2C/SPI interface, 

- A manual OUT dma channel  and an additional endpoint can be created. This channel and endpoint can then be used to transfer data received from FPGA to the USB Host.

-If an additional endpoint is not available, control endpoint(EP0) can be used. Here, vendor commands can be sent to the FX3 from the host and the data from the I2C/SPI interface can be sent to the USB Host through the control endpoint.

You could also refer to UsbI2cDmaMode and UsbI2cRegMode FX3 SDK examples.

Best Regards,
AliAsgar

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