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USB Superspeed Peripherals

PeterY
New Contributor

I want to implement two pairs of DMA. Based on the example slave fifosync, I have made the following extensions and created the corresponding DMA channel, but I can't see any endpoint

#define CY_FX_EP_PRODUCER_1               0x01    /* EP 1 OUT */
#define CY_FX_EP_PRODUCER_2               0x02    /* EP 2 OUT */

#define CY_FX_EP_CONSUMER_1               0x81    /* EP 1 IN */
#define CY_FX_EP_CONSUMER_2               0x82    /* EP 2 IN */
 
/* Producer socket used by the U-Port */
#define CY_FX_PRODUCER_1_USB_SOCKET     CY_U3P_UIB_SOCKET_PROD_0     /* USB Socket 1 is producer */
#define CY_FX_PRODUCER_2_USB_SOCKET     CY_U3P_UIB_SOCKET_PROD_1     /* USB Socket 2 is producer */

/* Consumer socket used by the U-Port */
#define CY_FX_CONSUMER_1_USB_SOCKET     CY_U3P_UIB_SOCKET_CONS_0    /* USB Socket 1 is consumer */
#define CY_FX_CONSUMER_2_USB_SOCKET     CY_U3P_UIB_SOCKET_CONS_1    /* USB Socket 2 is consumer */

/* Producer socket used by the P-Port */
#define CY_FX_PRODUCER_1_PPORT_SOCKET     CY_U3P_PIB_SOCKET_0     /* P-port Socket 1 is producer */
#define CY_FX_PRODUCER_2_PPORT_SOCKET     CY_U3P_PIB_SOCKET_1     /* P-port Socket 2 is producer */

/* Consumer socket used by the P-Port */
#define CY_FX_CONSUMER_1_PPORT_SOCKET     CY_U3P_PIB_SOCKET_2   /* P-port Socket 1 is CONSUMER */
#define CY_FX_CONSUMER_2_PPORT_SOCKET     CY_U3P_PIB_SOCKET_3   /* P-port Socket 2 is CONSUMER */
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1 Solution
JayakrishnaT_76
Moderator
Moderator

Hello,

For the device to enumerate with 4 endpoints, the descriptors need to be modified. With the default setting, the device enumerates with 2 bulk endpoints only (one IN and one OUT). If this default behaviour is to be changed, then the descriptor file (cyfxslfifousbdscr.c) needs to be changed. Inside this file, the following needs to be changed:

1. The interface descriptor 

2. New endpoint descriptors needs to be added.

3. The "Length of this descriptor and all sub descriptors" field of configuration descriptors should be changed.

Please try this and let me know if you are still facing enumeration issues.

Also, a few examples for the mapping between USB sockets and USB endpoints are given below:

CY_U3P_UIB_SOCKET_PROD_1 will be mapped to OUT endpoint 1 (0x01).

CY_U3P_UIB_SOCKET_CONS_1 will be mapped to IN endpoint 1 (0x81).

So, if you need to use 0x01 and 0x02 as USB OUT endpoints, then the corresponding sockets will be CY_U3P_UIB_SOCKET_PROD_1 and CY_U3P_UIB_SOCKET_PROD_2 respectively. Similarly if 0x81 and 0x82 needs to be used as IN endpoints, then CY_U3P_UIB_SOCKET_CONS_1 and CY_U3P_UIB_SOCKET_CONS_2 will be the respective sockets.  CY_U3P_UIB_SOCKET_PROD_0 and  CY_U3P_UIB_SOCKET_CONS_0 are mapped to the control endpoint. Please do not use these sockets for your project. Please make this modification in your project.

Best Regards,
Jayakrishna

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6 Replies
JayakrishnaT_76
Moderator
Moderator

Hello,

For the device to enumerate with 4 endpoints, the descriptors need to be modified. With the default setting, the device enumerates with 2 bulk endpoints only (one IN and one OUT). If this default behaviour is to be changed, then the descriptor file (cyfxslfifousbdscr.c) needs to be changed. Inside this file, the following needs to be changed:

1. The interface descriptor 

2. New endpoint descriptors needs to be added.

3. The "Length of this descriptor and all sub descriptors" field of configuration descriptors should be changed.

Please try this and let me know if you are still facing enumeration issues.

Also, a few examples for the mapping between USB sockets and USB endpoints are given below:

CY_U3P_UIB_SOCKET_PROD_1 will be mapped to OUT endpoint 1 (0x01).

CY_U3P_UIB_SOCKET_CONS_1 will be mapped to IN endpoint 1 (0x81).

So, if you need to use 0x01 and 0x02 as USB OUT endpoints, then the corresponding sockets will be CY_U3P_UIB_SOCKET_PROD_1 and CY_U3P_UIB_SOCKET_PROD_2 respectively. Similarly if 0x81 and 0x82 needs to be used as IN endpoints, then CY_U3P_UIB_SOCKET_CONS_1 and CY_U3P_UIB_SOCKET_CONS_2 will be the respective sockets.  CY_U3P_UIB_SOCKET_PROD_0 and  CY_U3P_UIB_SOCKET_CONS_0 are mapped to the control endpoint. Please do not use these sockets for your project. Please make this modification in your project.

Best Regards,
Jayakrishna

View solution in original post

PeterY
New Contributor

I have done all the content you mentioned. I can also see four endpoints, but I can't receive loopback data after sending data

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PeterY
New Contributor

If I using CY_U3P_PIB_SOCKET_0 as producer socket and CY_U3P_PIB_SOCKET_3 as consumer socket used by the P-Port,loopback is working properly.
but if I using CY_U3P_PIB_SOCKET_1 and Y_U3P_PIB_SOCKET_2,  I can't receive loopback data after sending data

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JayakrishnaT_76
Moderator
Moderator

Hello,

Please let us know the following information so that we can debug the issue further:

1. How is the loopback done. Please elaborate the loopback operation so that we can understand more about this issue. As per my understanding, the glChHandleSlFifoUtoP[0] and glChHandleSlFifoUtoP[1] are DMA channels that connects two OUT endpoint sockets with GPIF II consumer sockets. Similarly glChHandleSlFifoPtoU[0] and glChHandleSlFifoPtoU[1] are DMA channels that connects the GPIF II producer sockets with two IN endpoint sockets. Please let us know the datapath for the loopback operation.

2. Please let us know if you have modified the GPIF II project for realizing 4 sockets on the GPIF II side. The default GPIF II project supports 2 sockets only (i.e  CY_U3P_PIB_SOCKET_0 as producer socket and CY_U3P_PIB_SOCKET_3 as consumer socket). If you are using the default GPIF II project, then this could be the reason for the failure observed.

Best Regards,
Jayakrishna
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PeterY
New Contributor

Yes,I‘m using the default GPIF II project, I don't know how to modify and add socket to realizing 4 sockets on the GPIF II side.

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JayakrishnaT_76
Moderator
Moderator

Hello,

The selection of sockets is done by the FPGA by driving the address line (A1:0). GPIF II block of FX3 samples the address lines and accordingly drive/sample data to the corresponding sockets. So, no modification needs to be done on the state machine tab of the GPIF II designer project. But, the default GPIF II project makes use of 4 flags. Flag A and Flag B are dedicated ready and dedicated watermark flags respectively for thread 0. Whereas Flag C and Flag D are dedicated ready and dedicated watermark flags respectively for thread 3. 

As 4 threads are used in your application, this configuration needs to be changed. For starting the data transfer, ready flag needs to be used and for terminating the data transfer, watermark flag needs to be used. So, instead of 2 dedicated ready flags and 2 dedicated watermark flags, you can try using 1 current thread ready flag and 1 current thread watermark flag. More information on current/dedicated flags is already documented in Section 8 - Flag Configuration of the Application Note AN65974.

Also, the FPGA implementation should be also changed.  Table 4 of AN65974 shows the latencies associated with different flag configurations. Also Figure 6 of AN65974 shows Additional Latency Incurred at Start of Transfer When Using a Current Thread FLAG. These points should be noted while modifying the FPGA implementation. In addition to this, the FPGA being the master should drive the signals correctly for the loopback operation. Please let me know if you have any queries on this.

Best Regards,
Jayakrishna
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