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USB Superspeed Peripherals

agba_3844561
New Contributor II

Hello,

As the title states, I want to configure an SP605 board Over USB Using Cypress EZ-USB FX3.

I followed this tutorial http://www.cypress.com/documentation/application-notes/an84868-configuring-fpga-over-usb-using-cypre...

The same is for SP601 but they have equivalent pinout and same FPGA (Spartan-6) so I guessed it would work okay (using SP605 instead of SP601 in AN84868 - Configuring an FPGA over USB Using Cypress EZ-USB&#174... )

I have my out .bin file I created myself that is working perfectly with iMPACT platform (so I'm using that firmware for the FPGA).

I follow the instructions and get the following results:

error_program.png

After DONE LED is on, I click on configure. I see the INIT LED turning on for a second and then it stays on again permanently.

I didn't really find on the instructions when I am supposed to turn on the FPGA so I do it after downloading the firmware to the FX3.

I used the SP605 Hardware User Guide to know the equivalent leds/resistors to connect it to the SP605 board. The following images show my current set (PS: yellow cable is not used!).

IMG_20181126_150734.jpg

IMG_20181126_150744.jpg

IMG_20181126_150756.jpg

IMG_20181126_150815.jpg

Does anybody has any ideas of what it may be happening?

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1 Solution
SrinathS_16
Moderator
Moderator

Hello,

- The scope captures indicate that the CCLK is being output from the FPGA. Please ensure that you have configured the FPGA in Slave Serial configuration mode. This is done by setting the M[1:0] pins to 11.

- FX3 generates clock on the SCK pin (CCLK pin on FPGA) only when there is a data transfer. Please ensure that the firmware reaches the CyU3PSpiTransmitWords() API call for the clock to be generated. As I had mentioned in the previous interaction, comment out the below lines, disconnect the FPGA and then check for the clock on the SCK pin.

    CyU3PGpioSimpleGetValue (FPGA_INIT_B, &xFpga_Init_B);

  CyU3PGpioSimpleGetValue (FPGA_INIT_B, &xFpga_Init_B);

      if (xFpga_Init_B)

      {

          glConfigDone = CyFalse;

          return apiRetStatus;

      }

      CyU3PThreadSleep(10);

      /* Release PROG_B line */

      apiRetStatus |= CyU3PSpiSetSsnLine (CyTrue);

      CyU3PThreadSleep(10);  // Allow FPGA to startup

      /* Check if FPGA is now ready by testing the FPGA_Init_B signal */

      apiRetStatus |= CyU3PGpioSimpleGetValue (FPGA_INIT_B, &xFpga_Init_B);

      if( (xFpga_Init_B != CyTrue) || (apiRetStatus != CY_U3P_SUCCESS) ){

      return apiRetStatus;

      }

Best regards,

Srinath S

View solution in original post

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10 Replies
SrinathS_16
Moderator
Moderator

Hello,

- Can you please check if the GPIO[52] pin of FX3 is connected to the FPGA_INIT_B pin (one end of R69)? This is not clear from the image shared.

- Also, please probe the SPI_CLK, SPI_MOSI, SPI_SSN, GPIO[50] and GPIO[52] pins of FX3 and share the same.

- Kindly, ensure that you have placed pull-ups on the PROGRAM_B, INIT_B and DONE pins as they are open-drain configured.

- The FPGA drives the INIT_B LOW when the PROGRAM_B is pulsed LOW and is released during the configuration phase. So, the pull-up on the INIT_B takes effect and hence the INIT_B pin is at LOGIC HIGH during configuration. This is indicated by the INIT_LED turning OFF. If the INIT_B pin does not reach logic HIGH, the FX3 does not begin configuring the FPGA and will fail.

EDIT: Please ensure that you have configured the FPGA in Slave Serial configuration mode. This is done by setting the M[1:0] pins to 11.

Best regards,

Srinath S

agba_3844561
New Contributor II

Hello @Srinath S,

Thank you for your reply.

For items 1 and 2:

I used the following table to connect the pins,

table.png

SPI pins are equivalent on both boards (SP601 and SP605), I changed INIT_B and DONE using SP605 Hardware User Guide:

DoneInit.png

So yes, INIT_B is connected to pin 1 on resistor R69.

For the pins on the FX3 device I used the following schematic (Because the table states pins number of J7). However I didn't check it was GPIO[52] and so on. On the schematic (and the inscription of the board) it says I2C_WS or I2C_CLK for those pins:

schematic.png

Regarding the pull ups, you mean to add the pull ups on the FX3 firmware? I am using directly the ConfigFpgaSlaveFifoSync.img file configured, I haven't yet put hands on the code itself as I wanted first to see it work. You don't mean to add the pull up by hardware right?

I'll take my oscilloscope and try to debug the procedure you explained at last to see where the problem is.

Thank you again for your help.

Agustin Barrachina.

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agba_3844561
New Contributor II

I've used the oscilloscope and I indeed found something strange. Here the time diagram for a configure command:

General_Diagram.png

If I zoom to the clock signal:

Clock_floor.png

The minimum goes to 1.3 instead of 0 Volts (seams to be quite noisy as well).

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SrinathS_16
Moderator
Moderator

Hello,

After the PROGRAM_B pin is asserted, the INIT_B pin goes LOW. FX3 monitors the INIT_B pin and when it goes HIGH, FX3 starts configuring the FPGA. DONE pin goes HIGH when the configuration is successful. From the oscilloscope captures, I find that the INIT_B stays LOW and the DONE pin goes HIGH which is contradicting the expected behavior. Can you please confirm if the DONE and INIT_B pins are connected on the hardware as you have mentioned in the table?

Below is the expected waveform.

pastedImage_0.png

Best regards,

Srinath S

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agba_3844561
New Contributor II

Sorry, you are right. I did a program of python to generate the images from the csv saved with my oscilloscope.

Indeed the script had a bug and so the signal legends DONE<->INIT_B are mixed.

I didn't realized that because I debugged directly from the oscilloscope and just generated the images to post on the forum.

Here's the fixed image (I remade the measurements just to be sure):

General_Diagram_2.png

I also used the image you posted to debug the expected waveform and I for what I think, INIT_B, PROGRAM_B and DONE are as expected. I think INIT_B tension is not as high as PROGRAM_B because the pin has no enough current to power the LED + send the signal to the FX3 at the same time and so the tension falls a bit.

I think the problem lies with the clock signal.

Clock signal is a 2 MHz signal with a floor of 1.5 Volts which seems extremely high for me.

Clock_floor.png

Do you agree with my conclusion? If so, do you have any ideas on how to fix it?

Thank you again for all your help and sorry for the legends mistakes on the plots.

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SrinathS_16
Moderator
Moderator

Hello,

- Please let me know if you have made any changes to the AN84868 firmware. The firmware configures the SPI Clock to be 25MHz. In case you have not made any changes to the firmware, disconnect the FPGA and modify the firmware to comment out the below lines of code and probe the SPI clock line. Check if the clock is generated at 25MHz.

      CyU3PGpioSimpleGetValue (FPGA_INIT_B, &xFpga_Init_B);

      CyU3PGpioSimpleGetValue (FPGA_INIT_B, &xFpga_Init_B);

                if (xFpga_Init_B)

                {

                  glConfigDone = CyFalse;

                  return apiRetStatus;

                }

      CyU3PThreadSleep(10);

      /* Release PROG_B line */

      apiRetStatus |= CyU3PSpiSetSsnLine (CyTrue);

      CyU3PThreadSleep(10);   // Allow FPGA to startup

      /* Check if FPGA is now ready by testing the FPGA_Init_B signal */

    apiRetStatus |= CyU3PGpioSimpleGetValue (FPGA_INIT_B, &xFpga_Init_B);

    if( (xFpga_Init_B != CyTrue) || (apiRetStatus != CY_U3P_SUCCESS) ){

          return apiRetStatus;

    }

- Also, probe the data line and check if there is any data transfer.

- If possible, modify the firmware to include UART debug prints and share the logs.

Best regards,

Srinath S

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agba_3844561
New Contributor II

I've never touched the code. I used the .img file inside the bin folder that I downloaded directly from the zip file.

I'll do what you told me and come back if I have further knowledge on the issue.

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agba_3844561
New Contributor II

I've disconnected the CCLK signal from FX3 to the FPGA. I've measured that actually the FX3 CCLK output is always high and that the FPGA is outputting a 2 MHz clock! That's why the clock didn't get to 0 before. I've a double problem now.

Why doesn't the FX3 outputs the right clock? and why does the FPGA outputs a clock at all? I've double check that I was correctly using the SPIx4 and that I was using the correct pins and that I am also using the correct pins on the FX3 (with the pictures I uploaded it's possible to also check it here).

PROBE signals are the equivalent to the blue but from the FPGA part.

clk_comparison.png

Something similar happens with DIN:

din.png

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agba_3844561
New Contributor II

PS: I'll come back when I solve the issue or if I have more relevant data on the problem. I'll ask a colleague that has already worked with FX3 to see if you find what's wrong.

Thanks a lot.

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SrinathS_16
Moderator
Moderator

Hello,

- The scope captures indicate that the CCLK is being output from the FPGA. Please ensure that you have configured the FPGA in Slave Serial configuration mode. This is done by setting the M[1:0] pins to 11.

- FX3 generates clock on the SCK pin (CCLK pin on FPGA) only when there is a data transfer. Please ensure that the firmware reaches the CyU3PSpiTransmitWords() API call for the clock to be generated. As I had mentioned in the previous interaction, comment out the below lines, disconnect the FPGA and then check for the clock on the SCK pin.

    CyU3PGpioSimpleGetValue (FPGA_INIT_B, &xFpga_Init_B);

  CyU3PGpioSimpleGetValue (FPGA_INIT_B, &xFpga_Init_B);

      if (xFpga_Init_B)

      {

          glConfigDone = CyFalse;

          return apiRetStatus;

      }

      CyU3PThreadSleep(10);

      /* Release PROG_B line */

      apiRetStatus |= CyU3PSpiSetSsnLine (CyTrue);

      CyU3PThreadSleep(10);  // Allow FPGA to startup

      /* Check if FPGA is now ready by testing the FPGA_Init_B signal */

      apiRetStatus |= CyU3PGpioSimpleGetValue (FPGA_INIT_B, &xFpga_Init_B);

      if( (xFpga_Init_B != CyTrue) || (apiRetStatus != CY_U3P_SUCCESS) ){

      return apiRetStatus;

      }

Best regards,

Srinath S

View solution in original post

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