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USB Superspeed Peripherals

Anonymous
Not applicable

 Hello,

   

I am using FX3 as a Device controller used for USB3.0 communication wih a Host controller. So for data fetching i am interfacing FX3 with a processor on Slave-FIFO mode. 

   

So i am looking for documents so that i can configure the firmware code so as to use it as a Slave for data fetching.

   

Thanks

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Anonymous
Not applicable

Hi,

   

Please refer to the following application note on Slave FIFO interface. You can find the source code as an attachement to the same application note.

   

http://www.cypress.com/?rID=51581

   

Thanks,

   

sai krishna.

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Anonymous
Not applicable

 Hi,

   

I am on the PCB Designing stage of the Device Board using FX3. So it will be very helpfull if i get details regarding Design & Layout Guidelines for FX3.

   

Also i need help in following queries:

   

1. Stack Up details.

   

2. Standard Trace Width and Trace Spacing for USB3.0 & USB2.0 Differential Signals.

   

3. Impedance of GPIF signals.

   

 

   

Thanks

   

Vivek

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Anonymous
Not applicable

 And i am using Slave-FIFO in Synchronous mode for 16 bit Data line with 2 bit Address Bus.

   

So what all configuration i have to do inside Source Code for this?

   

Regards

   

Vivek

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Anonymous
Not applicable

Please refer to the following application note to get better idea on hardware design guidelines

   

http://www.cypress.com/?rID=53203

   

Regards,

   

sai krishna.

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Anonymous
Not applicable

 And i am using Slave-FIFO in Synchronous mode for 16 bit Data line with 2 bit Address Bus.

   

So what all configuration i have to do inside Source Code for this?

   

 

   

Pls reply ASAP

   

 

   

Thanks

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Anonymous
Not applicable

Hi,

   

 

   

You need to do the following change:

   

#define CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT (0) in cyfxslfifosync.h.

   

 

   

Also, please make sure that your GPIF II project is built by selecting the data bus width of 16-bit.

   

 

   

Thanks,

   

Sai Krishna.

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Anonymous
Not applicable

 Hi ,

   

I am doing Pre Routing Signal Integrity Analysis for the FX3 controller USB lines( TX , Rx and D+/-).

   

So in according to the EYE PATTERN specified in USB 3.0 architecture, we are getting proper eye pattern for RXp and RXn & D+ and D-.

   

But for TXp and TXn we are getting signals which are not over lapping to each other.

   

when I removed AC capacitor, both are over lapping each other.

   

I have attached image file for TX pairs with having AC capacitor and without AC capacitor.

   

So kindly help us whether the eye pattern are correct.

   

Thanks 

   

Vivek

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