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USB Superspeed Peripherals

WGT_4383351
New Contributor II

In the Master/Slave example of AN87216, the GPIF is configured to be one M2S and one S2M channel, both with the same buffer size and count.

How to configure GPIF in a more complex way:

1. More channels, like 5 channel, is more GPIF address like 3 bit address enought? Is there innate limit of GPIF channels? Remember there is something like "16 channel in total and only 1 channel per 4 channel".

2. Async channel:

channel 1: M2S 16KB*4

channel 2: S2M 1KB*4

channel 3: M2S 512B*2

channel 4: S2M 512B*2

channel 5: S2M 512B*2

Is there any GPIF designer examples for such configurations?

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1 Solution
JayakrishnaT_76
Moderator
Moderator

Hello,

Please go through the following Application Note which describes Slave FIFO interface using 5 bit addressing mode.

https://www.cypress.com/file/132506/download

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna

View solution in original post

53 Replies
JayakrishnaT_76
Moderator
Moderator

Hello,

Please go through the following Application Note which describes Slave FIFO interface using 5 bit addressing mode.

https://www.cypress.com/file/132506/download

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna

View solution in original post

WGT_4383351
New Contributor II

Are you sure that document is also about different configuration on different channels? Different cofiguration on different channel is more important than >4 channel.

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JayakrishnaT_76
Moderator
Moderator

Hello,

The Application note that I shared in my previous response is for making use of more than 4 sockets. The firmware for the same can be found in the following location of FX3 SDK

C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\slavefifo_examples

You can make use of slfifosync5bit or slfifoasync5bit project depending on your application. You can configure the DMA buffer size and the count for each channel depending on your requirement. Please go through the application note before making any edits in the firmware.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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WGT_4383351
New Contributor II

Is there some GPIF designer project for 2bit address and different DMA buffer size for different channels?

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JayakrishnaT_76
Moderator
Moderator

Hello,

For 2 bit addressing mode, you can refer to the application note AN65974. The link to the application note is given below:

https://www.cypress.com/file/136056/download

The project associated with this application note has 2 threads. One for external master to read data from the FX3's FIFO and the other for the external master to write data into FX3's FIFO. You can modify the size allocated for DMA channel in the firmware. At present, the size for the DMA buffers allocated to both the channels are the same. This is because the dmaCfg.size and dmaCfg.count are not changed after the creation of First channel. Please refer to the following code snippet:

pastedImage_2.png

As you can see, the dmaCfg.size and dmaCfg.count are not changed after the creation of DMA channel from U to P Port. If you want to change the size and count for the P to U Port channel, then update dmaCfg.size and dmaCfg.count just before the following statement:

dmaCfg.prodSckId = CY_FX_PRODUCER_PPORT_SOCKET;

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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WGT_4383351
New Contributor II

What about GPIF designer project? Shoudn't the project have more complex state machine, that set counters depend on GPIF threads? For one TX and one RX thread, the counter in GPIF read and write state machins can be modified independenly. But if there is 2 TX and 2 RX GPIF threads, and each have specific counter setting, how to designe the GPIF designer project - this is the main question.

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JayakrishnaT_76
Moderator
Moderator

Hello,

There is no GPIF II example project available for your requirement with us now. In the AN87216 example project, the thread switching is done by the master by driving the address lines A1:0. For the slave side, in all states, IN ADDR action is performed to sample the address lines and find the corresponding thread before performing the desired actions. So, the slave state machine need not be changed, but to implement your requirement the master state machine need to be changed. We do not have an example readily available for this as of now. You can try developing the state machine for master and we can support if you face any issues. You can refer to the documents in the following location for developing your own state machine:

C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\GPIFII_Designer

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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WGT_4383351
New Contributor II

"We do not have an example readily available for this as of now"

are you sure? Any cofiguration that need uses than 2 thread in one direction will need a master state machine that control the address[1:0] depend on the active thread. No such example means every example is for 1TX/1RX/1TX+1RX.

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JayakrishnaT_76
Moderator
Moderator

Hello,

Yes, we do not have an example that has more than one TX or RX threads.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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WGT_4383351
New Contributor II

When add a second master to slave branch, the condition is DMA_RDY_TH2, but there is error message in GPIF designer:

DMA_RDY_TH1 and DMA_RDY_TH2 cannot be used together in the outgoing equations from the state RD_WR_IDLE.

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WGT_4383351
New Contributor II

Can you design an example of master/slave that use all four GPIF threads, 2 M2S and 2 S2M threads?

There are already obstacles like early/late and related limitations, and now there is limitation about DMA thread conditions. More limits may come out in the future.

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JayakrishnaT_76
Moderator
Moderator

Hello,

Please find the modified state machine for master and slave along with the firmware projects for the same. The GPIF project for master is now made using same counter values for all the threads. Please note that the GPIF Designer only provides 3 counters : Data Counter, Addr Counter and CTRL Counter. So you can only use 3 counts at a time. This means that 2 DMA channels will have the same buffer size.

Please use one datapath at a time. That is M2S through one thread only. Use of more than one datapath might give you errors. Also, send full buffers only.

Please note that we currently do not have a setup to test these projects because do not have sufficient kits to test it with us at the moment. Please test this using your setup and let us know the results. Also make sure that the device is connected to a USB 3.0 port on host as the descriptors are modified only for Superspeed mode only.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
JayakrishnaT_76
Moderator
Moderator

Hello,

In addition to my previous response, please add the following lines of code below the statement CyU3PGpifSocketConfigure(1, CY_U3P_PIB_SOCKET_1, 0, CyFalse, 1); in the AutoSlave project.

1. CyU3PGpifSocketConfigure(2, CY_U3P_PIB_SOCKET_2, 4, CyFalse, 7);

2. CyU3PGpifSocketConfigure(3, CY_U3P_PIB_SOCKET_3, 0, CyFalse, 1);

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
WGT_4383351
New Contributor II

CyU3PGpifSocketConfigure

This is nice, are there other modifications needed that is outside the control of GPIF compiler?

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WGT_4383351
New Contributor II

In the master firmware:

    CyU3PGpifSocketConfigure(0, CY_U3P_PIB_SOCKET_0, 4, CyFalse, 1);

    CyU3PGpifSocketConfigure(1, CY_U3P_PIB_SOCKET_1, 4, CyFalse, 1);

In the slave firmware:

    CyU3PGpifSocketConfigure(0, CY_U3P_PIB_SOCKET_0, 4, CyFalse, 7);

    CyU3PGpifSocketConfigure(1, CY_U3P_PIB_SOCKET_1, 0, CyFalse, 1);

Why the parameters are different?

Will those parameter matter in this case? Will then affect performance?

I think it will be OK if the last parameter2^n<=COUNTER_for_that_channel right?

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JayakrishnaT_76
Moderator
Moderator

Hello,

The burst value refers to the logarithm to the base 2 of the burst size. You can change the burst value as needed. But while doing so make sure that the burst value does not exceed 14 as this is its maximum possible value. Also, the buffer size should be an integral multiple of the burst size.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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JayakrishnaT_76
Moderator
Moderator

Hello,

Even if the parameters are different, it will not affect the performance. The first two parameters are used for mapping the socket with the thread and the remaining are used for partial flags. This project does not make use of partial flags. So it should not cause any issues.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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WGT_4383351
New Contributor II

Here is the initial test result:

setup:

CY_FX_DMA_SIZE_MULTIPLIER is not used (=1)

master EP1IN - GPIF thread 0 - GPIF - GPIF thread 0 slave EP1OUT SZ=1024 BL=4 BULK 4KB*4 buffers

master EP1OUT - GPIF thread 1 - GPIF - GPIF thread 1 slave EP1IN SZ=1024 BL=16 BULK 16KB*4 buffers

master EP2IN - GPIF thread 2 - GPIF - GPIF thread 2 slave EP2OUT SZ=256 BL=1 INT 256*4 buffers

master EP3OUT - GPIF thread 3 - GPIF - GPIF thread 3 slave EP3IN SZ=256 BL=1 INT 256*4 buffers

Master short packet states are removed too (in your GPIF project master short packet states is preserved).

Now the behavior is:

When send 1 packet by Control Center to slave (4KB to EP1OUT or 256B to EP2OUT):

1. no CY_U3P_DMA_CB_CONS_EVENT

2. there are 4 CY_U3P_DMA_CB_PROD_EVENT on master

5. After the send, master can receive infinite packets (4KB from EP1IN or 256B from EP2IN)

4. Can only send once, for the second send there won't be CY_U3P_DMA_CB_PROD_EVENT  on master any more

Conclusion1: When send 1 packet to slave, the GPIF state machine get stuck in some sending states and continue to send.

When send 1 packet by Control Center to master(16KB to EP1OUT or 256B to EP3OUT):

1. There is 1 CY_U3P_DMA_CB_CONS_EVENT on master

2. There is no CY_U3P_DMA_CB_PROD_EVENT on slave

3. Slave can't receive packet

4. GPIF state machine is not dead, can repeat this operation

Conclusion2: The data sent to master get consumed by GPIF, but there is no data produced on the GPIF on slave - when can this happen?

All DMA type are CY_U3P_DMA_TYPE_AUTO_SIGNAL to capture events.

Only GPIF side events are registered to dmaCfg.notification, USB side event is not considered (not needed)

Conclusion3: Both the branch after SELECT1_OR_2 can be entered, but there is problem in the read/write sub braches.

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WGT_4383351
New Contributor II

To make the above post more clear:

.....

When send 1 packet by Control Center to slave (4KB to EP1OUT or 256B to EP2OUT):

1. no CY_U3P_DMA_CB_CONS_EVENT on slave

......

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WGT_4383351
New Contributor II

To make the above post more clear:

......

5. After the send, master can receive infinite packets (4KB from EP1IN or 256B from EP2IN)

     But there are only 4 CY_U3P_DMA_CB_PROD_EVENT on master, there is no more CY_U3P_DMA_CB_PROD_EVENT on master,although master can continue to receive infinite packets.

......

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WGT_4383351
New Contributor II

pastedImage_0.png

Is this warning a problem?

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WGT_4383351
New Contributor II

According to your master state machine:

Write0       DMA_RDY_TH1|FLAG_A -> DMA_RDY_TH1&FLAG_B

Read0        DMA_RDY_TH1|FLAG_A ->FLAG_A

Write1    LOGIC_ONE   ->       DMA_RDY_TH3&FLAG_D

Read1     LOGIC_ONE       ->!DMA_RDY_TH3&FLAG_C

This seems to be not symmetric and confusing: check FLAG_A then FLAG_B? No thread 2 and 0 checking?

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WGT_4383351
New Contributor II

The ideal one is like:

T0RDY&A->write0

T1RDY&B->read0

T2RDY&C->write1

T3RDY&D->read1

But there are limitations to forbid something beautiful like the above.

Did you mean complex trick is needed, and the result state machine will be look wrong at the first glance, but is right if you dig in?

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WGT_4383351
New Contributor II

Even more ideal one will consider priority between channels:

T0RDY&A->write0

T1RDY&B & !(T0RDY&A)->read0

T2RDY&C & !(T0RDY&A) & !(T1RDY&B)->write1

T3RDY&D & !(T0RDY&A) & !(T1RDY&B) & !(T2RDY&C)->read1

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JayakrishnaT_76
Moderator
Moderator

Hello,

In the master state machine that was shared, when the state machine reaches the state SELECT_1_OR_2, it has 2 options:

1. Either to switch to RD_WR_IDLE, transition equation: DMA_RDY_TH1|FLAG_A

2. Or to switch to RD_WR_IDLE_1, transition equation: LOGIC_ONE

Now consider the following cases:

1. DMA_RDY_TH1 or FLAG_A is not asserted: In this case, the state machine directly switches to RD_WR_IDLE_1. After this switch, the state machine can get stuck in RD_WR_IDLE_1 if FLAG_C or DMA_RDY_TH3 is not asserted. To eliminate such a case, another state transition from RD_WR_IDLE_1 to SELECT_1_OR_2 is given with transition equation as !DMA_RDY_TH3&!FLAG_C.

2. DMA_RDY_TH1 or FLAG_A is asserted: In this case, both the transition equations will be true and the state machine switches to RD_WR_IDLE. The explanation for the same can be found in response 5 of the thread whose link is given below:

GPIF thread arbitration

From the states RD_WR_IDLE and RD_WR_IDLE_1, the state machine operation is similar to that in the master example except that the action of watermark flag is removed.

Please let me know if you have any queries on this.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
WGT_4383351
New Contributor II

Now I see your state machine is indeed clear and symmetric.

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WGT_4383351
New Contributor II

Now there is a serious problem, every time I modify a LD_DATA_COUNT or LD_ADDR_COUNT, every LD_DATA_COUNT or LD_ADDR_COUNT in the state machine is changed - there seems only can be one setting for these value. Is this a bug of the GPIF designer?

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JayakrishnaT_76
Moderator
Moderator

Hello,

This is a limitation of GPIF Designer. You can only set a limit value for a particular counter through GPIF Designer. If you use the same counter in another state, the same limit value will be used in that state also. You can use 3 different counts (3 different DMA buffer sizes) by making use of CTRL_COUNT. You can remove either DATA_COUNT or ADDR_COUNT from RD_WR_IDLE or RD_WR_IDLE_1 state and use CTRL_COUNT instead of it. This will help you to use 3 count values in the state machine (or 3 different DMA buffer sizes). That means 2 channels between master and slave will have the same DMA buffer size. As you might be knowing, while making use of CTRL_COUNT instead of DATA_COUNT or ADDR_COUNT, ensure that the transition equations and actions in subsequent states where counters are used are modified properly to avoid any errors.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
WGT_4383351
New Contributor II

Did you mean DATA_COUNT has nothing todo with data and ADDR_COUNT has nothing to do with address, they are just counter with names?

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JayakrishnaT_76
Moderator
Moderator

Hello,

Yes, they are just counters with names.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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WGT_4383351
New Contributor II

Then they are better to be named as COUNTER_x

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JayakrishnaT_76
Moderator
Moderator

Hello,

Thank you for your suggestion. I will discuss about it internally.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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WGT_4383351
New Contributor II

There is CMP_CTRL and CMP_DATA, but no CMP_ADDR, then ctrl counter and data counter are more advanced counter than addr counter?

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JayakrishnaT_76
Moderator
Moderator

Hello,

Regarding your query in response 27, the action CMP_ADDR can only be used if you are using IN_ADDR. We are not using address bus in this project. Hence IN_ADDR is not available and therefore CMP_ADDR is also not available. You can find it available in the slave's project. This is documented in the GPIF II userguide at page 37. This document can be found in the following location:

C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\GPIFII_Designer

Regarding your query in response 28, I didn't understand what exactly you meant by priority. When the state machine is in a particular state, it will switch to the next state if the transition equation is met. If both transition equations are met, then it will switch to the left state as discussed before. In the state RD_WR_IDLE_1, either read or write from FIFO can be done. The switch is done on the basis of availability of buffers in slave and master by checking the flags. So I dont understand what exactly you meant by priority. Also, the state RD_WR_IDLE_1 has more than 2 transition equations. So mirror states are used for building the state machine. If you change the transition equations from this state, then it can throw errors.

Regarding your query in response 29, the conditions are evaluated at edges of the PCLK. Suppose you are in Select_1_OR_2 state. There are two options for the state machine to carry forward. Suppose in the next PCLK, the condition to switch to RD_WR_IDLE is not met, then it will switch to RD_WR_IDLE_1 and come back in the next PCLK to Select_1_OR_2 state. By this time, the condition to switch to RD_WR_IDLE will be met.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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WGT_4383351
New Contributor II

My Response 28:

Priority: suppose there are 4 channels through GPIF between master and slave. A channel with higher priority means if that channel has data to transfer, other channels with lower priority's states won't be entered.

So your GPIF design means WR_FLAG_1 has higher priority than DR_ADDR_1, since the condition to DR_ADDR_1 is !DMA_RDY_TH3&FLAG_C which means if there is data to transfer on channel 3, channel 2 's states won't be entered.

My Response 29:

"

Suppose in the next PCLK, the condition to switch to RD_WR_IDLE is not met, then it will switch to RD_WR_IDLE_1 and come back in the next PCLK to Select_1_OR_2 state. By this time, the condition to switch to RD_WR_IDLE will be met.

"

My meaning was, if the condition to RD_WR_IDLE is met, since the condition to RD_WR_IDLE_1 (LOGIC_ONE) is also met, how to decide the next state? How can you be sure RD_WR_IDLE is the next state? I forget what did you mean by "the left state"? How can you be sure RD_WR_IDLE is the "left state"?

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JayakrishnaT_76
Moderator
Moderator

Hello,

"So your GPIF design means WR_FLAG_1 has higher priority than DR_ADDR_1, since the condition to DR_ADDR_1 is !DMA_RDY_TH3&FLAG_C which means if there is data to transfer on channel 3, channel 2 's states won't be entered."

In this case, the state machine will go to WR_FLAG_1 and complete execution and return back to RD_WR_IDLE_1. Now, DMA_RDY_TH3 should be low. So if FLAGC is high, the state machine can follow the other path and go to DR_ADDR_1. If you do not want this to happen,

you can try something as shown in the following snapshot.

pastedImage_0.png

I have added a STATE3 in between SELECT_1_OR_2. The transition equation from SELECT_1_OR_2 to STATE3 is LOGIC_ONE and the reverse is !DMA_RDY_TH3&!FLAG_C. The transition equation from STATE3 to RD_WR_IDLE_1 is DMA_RDY_TH3|FLAG_C. If you modify the state machine like this, you can modify the transition equation from RD_WR_IDLE_1 to DR_ADDR_1 as just FLAG_C and GPIF Designer will not show any error.

Regarding your question in response 29, if the state machine is in a particular state and if both the transition equations are met, then it will undergo a transition to the left state. The left state and right state of a particular state can be identified from the .h file generated by the GPIF Designer. For this, you need to look into CyFxGpifWavedata structure in the generated .h file. The snapshot of the structure for this project is attached as a snapshot below:

pastedImage_2.png

You need to check the 12 bytes on left to find the details about left state and the 12 bytes on right to find the details about right state. Now, the fields that are enclosed in the box indicates the left and right states as shown below.

pastedImage_3.png

The first row represents start state. So the left state is 0x01. The macro SELECT_1_OR_2 is 1. This means the left state for start state is SELECT_1_OR_2. The right state is 00 this means start state is not having a right state. Now take the second row. This row is for state SELECT_1_OR_2. The left state for this is 0x02 and right state is 0x0B. The macro RD_WR_IDLE is 2 and macro RD_WR_IDLE_1 is 11. This means that the left state for state SELECT_1_OR_2 is RD_WR_IDLE and right state is RD_WR_IDLE_1.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
WGT_4383351
New Contributor II

Nice, and dialog during build disappears.

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JayakrishnaT_76
Moderator
Moderator

Hello,

Yes, this is because in the state machine that was shared before, there were 3 transitions from RD_WR_IDLE_1 state. So mirror states were used for building the project. But in this state machine, only 2 transitions are there from RD_WR_IDLE_1 state. So the mirror states are not required. Hence you dont see the warning.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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WGT_4383351
New Contributor II

"

In this case, the state machine will go to WR_FLAG_1 and complete execution and return back to RD_WR_IDLE_1. Now, DMA_RDY_TH3 should be low. So if FLAGC is high, the state machine can follow the other path and go to DR_ADDR_1

"

This also means, due to the work-break behavior of DMA_RDY_TH*, the default is round robin arbitration. To implement true priority, a repeated wait state need to be added to the end of higher priority chain, to make sure there is no more data to transfer on that higher priority channel.

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