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USB Superspeed Peripherals

JaMa_1550451
New Contributor II

I have a CYUSB3KIT connected to a Xilinx KC705 eval board.  I updated the AN65974 app note to work with Vivado 2020.1.  I build slaveFIFO2b_fpga and the image seems good.

So my issue:

I seem to be able to do the loopback test fine.  I send a file, and then I can receive the data back using the USB Control Center.  I then continued with the examples in the AN65974 app note and could not get BULK IN to work.  Here are the steps I do.

  1. Power up the FPGA with the switches all set to zero (I am using SW11 on the KC705)
  2. flash the RAM on the FX3 to use the pre-compiled SF_streamIN.img
  3. flash the KC705 with my slaveFIFO2b_fpga
  4. set the switch to be OFF, OFF, ON, ON (FPGA continuously writes full packets)
  5. In the USB Control Center I hit the "Reconnect Device" button so that the FX3 is in the BULK IN mode
  6. IN the C++ Streamer app, I select the Cypress FX3 USB StreamerExample device and choose the BULK IN endpoint
  7. I set the packets for transfer to be 128 and the transfer to queue to be 32 (just like the app note) and click start
  8. All I get is failed packets:

pastedImage_2.png

Following the same steps (still using the same img file for the FX3, but setting the jumpers to OFF, ON, OFF, OFF and choosing BULK OUT in the C++ stream seems to work great:

pastedImage_3.png

So what am I missing?  I checked and the PMODE flags are toggling as they should as I flip the different switches.  I am not sure what else I should be looking into next.

0 Likes
1 Solution
Rashi_Vatsa
Moderator
Moderator

Hello,

From the traces, I see that Flag B is LOw which is not expected. Initially, both the flags A and B should be HIGH i.e. after programming the FX3 which indicates that the DMA buffers (FX3) are ready to receive the data from the FPGA (master).

The FPGA code checks for both the flags to be high and only then it will assert the SLWR signal. As seen in the trace, SLWR is HIGH always which means the FPGA is not writing the data to FX3. For FPGA to assert SLWR LOW (Write data to FX3) both the Flags i.e. FLAG A &B  should be HIGH.

This is the code snippet from the default FPGA code provided with the Application note AN65974

fpga_write.PNG

- Please let me know if you have changed the GPIF state machine using the GPIF designer tool or any firmware changes are done as the UART debug prints are not as per the default firmware.

- Also, confirm if any changes done in the default FPGA code

- If you are using the default  FX3 firmware and default FPGA code. Please check if the following

1) Flag B signal is not pulled low internally from the FPGA side

2) Please check the initial condition i.e. Program the FX3 > program the FPGA (set the switches for selecting Stream IN) and then check the initial signals again.

Please let me know if any queries on this

Regards,

Rashi

Regards,
Rashi

View solution in original post

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4 Replies
Rashi_Vatsa
Moderator
Moderator

Hello,

Please let me know if you can probe the FPGA- FX3 interface signals using the Integrated Logic Analyzer.

We can check if the signals like fdata, flags (flag a,b,c,d) mode_p,slcs, sloe are working as expected. Please probe these lines and share the results.

- Also, please share the UART debug prints to check if the data received on FX3

Regards,

Rashi

Regards,
Rashi
JaMa_1550451
New Contributor II

OK, When I attempt to do the bulk transfer, this is the state of the various flags and signals:

pastedImage_0.png

I am not 100% sure what to make of it, so I need to read up on the various items to see if something pops out.

I have been so far unable to get anything out of the UART, so I can't capture any debug.  I will keep trying.

0 Likes
JaMa_1550451
New Contributor II

Actually, I was able to get a little debug out.  Two comms ports show up in TeraTerm, but only one shows debug.  All that streams across is a corruption check.  Nothing changes when I try to run the app:

Loopback thread: 10

MemAlloc Buffer: 4003A6D8

MemAlloc Buffer: 4003A62C

MemAlloc Buffer: 4003A200

MemAlloc Buffer: 40039DD4

MemAlloc Buffer: 40039D68

MemAlloc Buffer: 4003993C

MemAlloc Buffer: 40039890

MemAlloc Buffer: 40039664

MemAlloc Buffer: 40038E38

MemAlloc Buffer: 40038A0C

MemAlloc Buffer: 400385E0

MemAlloc Buffer: 400383B4

MemAlloc Buffer: 40038008

BufAlloc Buffer: 40042C60

BufAlloc Buffer: 40042820

BufAlloc Buffer: 400423E0

BufAlloc Buffer: 40041FA0

BufAlloc Buffer: 40041B60

BufAlloc Buffer: 40041720

BufAlloc Buffer: 400412E0

BufAlloc Buffer: 40040EA0

BufAlloc Buffer: 40040C60

BufAlloc Buffer: 40040A20

BufAlloc Buffer: 400408E0

BufAlloc Buffer: 400407A0

BufAlloc Buffer: 40040660

BufAlloc Buffer: 40040520

BufAlloc Buffer: 400403E0

BufAlloc Buffer: 400402A0

BufAlloc Buffer: 40040160

BufAlloc Buffer: 40040020

Corruption check done

Loopback thread: 11

MemAlloc Buffer: 4003A6D8

MemAlloc Buffer: 4003A62C

MemAlloc Buffer: 4003A200

MemAlloc Buffer: 40039DD4

MemAlloc Buffer: 40039D68

MemAlloc Buffer: 4003993C

MemAlloc Buffer: 40039890

MemAlloc Buffer: 40039664

MemAlloc Buffer: 40038E38

MemAlloc Buffer: 40038A0C

MemAlloc Buffer: 400385E0

MemAlloc Buffer: 400383B4

MemAlloc Buffer: 40038008

BufAlloc Buffer: 40042C60

BufAlloc Buffer: 40042820

BufAlloc Buffer: 400423E0

BufAlloc Buffer: 40041FA0

BufAlloc Buffer: 40041B60

BufAlloc Buffer: 40041720

BufAlloc Buffer: 400412E0

BufAlloc Buffer: 40040EA0

BufAlloc Buffer: 40040C60

BufAlloc Buffer: 40040A20

BufAlloc Buffer: 400408E0

BufAlloc Buffer: 400407A0

BufAlloc Buffer: 40040660

BufAlloc Buffer: 40040520

BufAlloc Buffer: 400403E0

BufAlloc Buffer: 400402A0

BufAlloc Buffer: 40040160

BufAlloc Buffer: 40040020

Corruption check done

Loopback thread: 12

MemAlloc Buffer: 4003A6D8

MemAlloc Buffer: 4003A62C

MemAlloc Buffer: 4003A200

MemAlloc Buffer: 40039DD4

MemAlloc Buffer: 40039D68

MemAlloc Buffer: 4003993C

MemAlloc Buffer: 40039890

MemAlloc Buffer: 40039664

MemAlloc Buffer: 40038E38

MemAlloc Buffer: 40038A0C

MemAlloc Buffer: 400385E0

MemAlloc Buffer: 400383B4

MemAlloc Buffer: 40038008

BufAlloc Buffer: 40042C60

BufAlloc Buffer: 40042820

BufAlloc Buffer: 400423E0

BufAlloc Buffer: 40041FA0

BufAlloc Buffer: 40041B60

BufAlloc Buffer: 40041720

BufAlloc Buffer: 400412E0

BufAlloc Buffer: 40040EA0

BufAlloc Buffer: 40040C60

BufAlloc Buffer: 40040A20

BufAlloc Buffer: 400408E0

BufAlloc Buffer: 400407A0

BufAlloc Buffer: 40040660

BufAlloc Buffer: 40040520

BufAlloc Buffer: 400403E0

BufAlloc Buffer: 400402A0

BufAlloc Buffer: 40040160

BufAlloc Buffer: 40040020

Corruption check done

Loopback thread: 13

MemAlloc Buffer: 4003A6D8

MemAlloc Buffer: 4003A62C

MemAlloc Buffer: 4003A200

MemAlloc Buffer: 40039DD4

MemAlloc Buffer: 40039D68

MemAlloc Buffer: 4003993C

MemAlloc Buffer: 40039890

MemAlloc Buffer: 40039664

MemAlloc Buffer: 40038E38

MemAlloc Buffer: 40038A0C

MemAlloc Buffer: 400385E0

MemAlloc Buffer: 400383B4

MemAlloc Buffer: 40038008

BufAlloc Buffer: 40042C60

BufAlloc Buffer: 40042820

BufAlloc Buffer: 400423E0

BufAlloc Buffer: 40041FA0

BufAlloc Buffer: 40041B60

BufAlloc Buffer: 40041720

BufAlloc Buffer: 400412E0

BufAlloc Buffer: 40040EA0

BufAlloc Buffer: 40040C60

BufAlloc Buffer: 40040A20

BufAlloc Buffer: 400408E0

BufAlloc Buffer: 400407A0

BufAlloc Buffer: 40040660

BufAlloc Buffer: 40040520

BufAlloc Buffer: 400403E0

BufAlloc Buffer: 400402A0

BufAlloc Buffer: 40040160

BufAlloc Buffer: 40040020

Corruption check done

0 Likes
Rashi_Vatsa
Moderator
Moderator

Hello,

From the traces, I see that Flag B is LOw which is not expected. Initially, both the flags A and B should be HIGH i.e. after programming the FX3 which indicates that the DMA buffers (FX3) are ready to receive the data from the FPGA (master).

The FPGA code checks for both the flags to be high and only then it will assert the SLWR signal. As seen in the trace, SLWR is HIGH always which means the FPGA is not writing the data to FX3. For FPGA to assert SLWR LOW (Write data to FX3) both the Flags i.e. FLAG A &B  should be HIGH.

This is the code snippet from the default FPGA code provided with the Application note AN65974

fpga_write.PNG

- Please let me know if you have changed the GPIF state machine using the GPIF designer tool or any firmware changes are done as the UART debug prints are not as per the default firmware.

- Also, confirm if any changes done in the default FPGA code

- If you are using the default  FX3 firmware and default FPGA code. Please check if the following

1) Flag B signal is not pulled low internally from the FPGA side

2) Please check the initial condition i.e. Program the FX3 > program the FPGA (set the switches for selecting Stream IN) and then check the initial signals again.

Please let me know if any queries on this

Regards,

Rashi

Regards,
Rashi

View solution in original post

0 Likes