cancel
Showing results for 
Search instead for 
Did you mean: 

USB Superspeed Peripherals

Anonymous
Not applicable

Just like FTDI FT600Q-FT601Q(USB 3.0 to FIFO Bridge).

Is that possible to configure FX3 to receive video stream from Host, and then output parallel data via GPIF II.

Design GPIF to support : ((Parallel FIFO bus clock / Control signal / data bus output)

EX:

- output Pixel clk

- output FV( Vsync )

- output LV( Hsync )

- output Data bus (8 ~16bits)

0 Likes
Reply
1 Solution
Anonymous
Not applicable

Hi,

Such an implementation may sound feasible, but there may be many issues in practical realization. This has not been tested before. The FV, LV synchronization on the GPIF lines with respect to the lines and frame ending is not possible to achieve with accuracy.

Regards,

-Madhu Sudhan

View solution in original post

0 Likes
Reply
2 Replies
Anonymous
Not applicable

Hi,

Such an implementation may sound feasible, but there may be many issues in practical realization. This has not been tested before. The FV, LV synchronization on the GPIF lines with respect to the lines and frame ending is not possible to achieve with accuracy.

Regards,

-Madhu Sudhan

View solution in original post

0 Likes
Reply
Anonymous
Not applicable

Yes its possible. We have supported a customer to design a MIPI based secondary display through USB. This design had a vendor driver in the Host PC, FX3 device connected to parallel to MIPI bridge and a MIPI to MIPI bridge to control the frame rate, brightness, etc. of the MIPI display.

As Madhu said, the rate matching has to be done and this is done by the MIPI to MIPI bridge. FX3 can generate the FV, LV signals but the clock signal will be derived from FX3 SYS_CLOCK (~400MHz) through dividers and this clock value may or may not serve the purpose.

Regards,

Savan

0 Likes
Reply